| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-10-07 | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() | Frank Chang | 2 | -13/+21 |
| 2021-10-07 | target/riscv: Remove RVB (replaced by Zb[abcs]) | Philipp Tomsich | 3 | -33/+0 |
| 2021-10-07 | target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh | Philipp Tomsich | 2 | -77/+21 |
| 2021-10-07 | target/riscv: Add rev8 instruction, removing grev/grevi | Philipp Tomsich | 4 | -79/+15 |
| 2021-10-07 | target/riscv: Add a REQUIRE_32BIT macro | Philipp Tomsich | 1 | -0/+6 |
| 2021-10-07 | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci | Philipp Tomsich | 4 | -55/+18 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbb-extension | Philipp Tomsich | 2 | -41/+50 |
| 2021-10-07 | target/riscv: Add instructions of the Zbc-extension | Philipp Tomsich | 4 | -1/+65 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbs-extension | Philipp Tomsich | 2 | -18/+24 |
| 2021-10-07 | target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) | Philipp Tomsich | 2 | -78/+0 |
| 2021-10-07 | target/riscv: Remove the W-form instructions from Zbs | Philipp Tomsich | 2 | -63/+0 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zba-extension | Philipp Tomsich | 2 | -13/+23 |
| 2021-10-07 | target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties | Philipp Tomsich | 2 | -0/+8 |
| 2021-10-07 | target/riscv: clwz must ignore high bits (use shift-left & changed logic) | Philipp Tomsich | 1 | -3/+5 |
| 2021-10-07 | target/riscv: fix clzw implementation to operate on arg1 | Philipp Tomsich | 1 | -1/+1 |
| 2021-10-07 | target/riscv: Introduce temporary in gen_add_uw() | Philipp Tomsich | 1 | -2/+4 |
| 2021-09-21 | hw/core: Make do_unaligned_access noreturn | Richard Henderson | 1 | -1/+1 |
| 2021-09-21 | include/exec: Move cpu_signal_handler declaration | Richard Henderson | 1 | -2/+0 |
| 2021-09-21 | target/riscv: csr: Rename HCOUNTEREN_CY and friends | Bin Meng | 2 | -16/+16 |
| 2021-09-21 | target/riscv: Backup/restore mstatus.SD bit when virtual register swapped | Frank Chang | 1 | -1/+2 |
| 2021-09-21 | target/riscv: Expose interrupt pending bits as GPIO lines | Alistair Francis | 1 | -0/+30 |
| 2021-09-21 | target/riscv: Fix satp write | LIU Zhiwei | 1 | -1/+1 |
| 2021-09-21 | target/riscv: Update the ePMP CSR address | Alistair Francis | 2 | -2/+3 |
| 2021-09-14 | target/riscv: Restrict cpu_exec_interrupt() handler to sysemu | Philippe Mathieu-Daudé | 3 | -7/+2 |
| 2021-09-14 | accel/tcg: Add DisasContextBase argument to translator_ld* | Ilya Leoshkevich | 1 | -2/+3 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson | 2 | -61/+26 |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson | 2 | -210/+57 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson | 1 | -65/+60 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson | 1 | -76/+70 |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson | 1 | -13/+6 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson | 1 | -28/+19 |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson | 3 | -66/+132 |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson | 1 | -18/+8 |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson | 1 | -8/+15 |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson | 1 | -18/+20 |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson | 1 | -15/+10 |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson | 1 | -2/+12 |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson | 3 | -202/+125 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson | 2 | -23/+15 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson | 2 | -233/+234 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson | 2 | -127/+127 |
| 2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson | 1 | -22/+18 |
| 2021-09-01 | target/riscv: Remove gen_arith_div* | Richard Henderson | 2 | -50/+8 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_arith* | Richard Henderson | 4 | -90/+64 |
| 2021-09-01 | target/riscv: Introduce DisasExtend and new helpers | Richard Henderson | 1 | -16/+81 |
| 2021-09-01 | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr | Richard Henderson | 9 | -144/+144 |
| 2021-09-01 | target/riscv: Clean up division helpers | Richard Henderson | 1 | -83/+91 |
| 2021-09-01 | target/riscv: Use tcg_constant_* | Richard Henderson | 3 | -70/+34 |
| 2021-09-01 | target/riscv: Add User CSRs read-only check | LIU Zhiwei | 1 | -3/+5 |
| 2021-09-01 | target/riscv: Don't wrongly override isa version | LIU Zhiwei | 1 | -6/+8 |
