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2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li3-2/+62
2020-08-21target/riscv: Fix the translation of physical addressZong Li1-2/+3
2020-08-21riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying1-3/+2
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei2-8/+8
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei1-5/+1
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2-16/+73
2020-08-21target/riscv: Check nanboxed inputs to fp helpersRichard Henderson2-18/+57
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson1-0/+4
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2-15/+12
2020-08-21target/riscv: Generate nanboxed results from fp helpersRichard Henderson2-19/+28
2020-08-21meson: targetPaolo Bonzini3-30/+36
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini10-14/+14
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini1-0/+1
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth1-2/+2
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li1-1/+1
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei1-1/+9
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei1-0/+1
2020-07-13target/riscv: Fix pmp NA4 implementationAlexandre Mergnat1-1/+1
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang1-1/+1
2020-07-13target/riscv: fix return value of do_opivx_widen()Frank Chang1-1/+1
2020-07-13target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang1-1/+1
2020-07-13target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang1-0/+5
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2-1/+46
2020-07-02target/riscv: vector compress instructionLIU Zhiwei4-0/+64
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei4-0/+150
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei4-0/+155
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei2-0/+52
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei3-0/+67
2020-07-02target/riscv: integer extract instructionLIU Zhiwei2-0/+117
2020-07-02target/riscv: vector element index instructionLIU Zhiwei4-0/+56
2020-07-02target/riscv: vector iota instructionLIU Zhiwei4-0/+62
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei4-0/+98
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei4-0/+54
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei4-0/+55
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei4-0/+92
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei4-0/+54
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei4-0/+58
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei4-0/+24
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei4-0/+133
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei4-0/+103
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei4-0/+106
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei4-0/+56
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei4-0/+68
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei6-30/+107
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei4-0/+258
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei4-0/+118
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei4-0/+50
2020-07-02target/riscv: vector floating-point square-root instructionLIU Zhiwei4-0/+93
2020-07-02target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei4-0/+126
2020-07-02target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei4-0/+334
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