riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-05-18	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson	1	-5/+7
2018-05-17	target/riscv: Remove floatX_maybe_silence_nan from conversions	Richard Henderson	1	-4/+2
2018-05-11	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...	Peter Maydell	1	-49/+17
2018-05-10	target/riscv: Use new atomic min/max expanders	Richard Henderson	1	-49/+17
2018-05-09	target/riscv: convert to TranslatorOps	Emilio G. Cota	1	-78/+80
2018-05-09	target/riscv: convert to DisasContextBase	Emilio G. Cota	1	-65/+64
2018-05-09	target/riscv: convert to DisasJumpType	Emilio G. Cota	1	-44/+28
2018-05-09	target/riscv: avoid integer overflow in next_page PC check	Emilio G. Cota	1	-3/+3
2018-05-06	RISC-V: No traps on writes to misa,minstret,mcycle	Michael Clark	1	-12/+13
2018-05-06	RISC-V: Make mtvec/stvec ignore vectored traps	Michael Clark	1	-6/+8
2018-05-06	RISC-V: Add mcycle/minstret support for -icount auto	Michael Clark	2	-2/+28
2018-05-06	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	Michael Clark	2	-18/+50
2018-05-06	RISC-V: Allow S-mode mxr access when priv ISA >= v1.10	Michael Clark	1	-2/+5
2018-05-06	RISC-V: Clear mtval/stval on exceptions without info	Michael Clark	1	-0/+8
2018-05-06	RISC-V: Hardwire satp to 0 for no-mmu case	Michael Clark	1	-2/+5
2018-05-06	RISC-V: Update E and I extension order	Michael Clark	2	-1/+2
2018-05-06	RISC-V: Remove erroneous comment from translate.c	Michael Clark	1	-1/+0
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark	1	-1/+0
2018-03-29	RISC-V: Workaround for critical mstatus.FS bug	Michael Clark	1	-2/+15
2018-03-28	RISC-V: Convert cpu definition to future model	Michael Clark	1	-54/+69
2018-03-20	Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...	Peter Maydell	1	-0/+1
2018-03-20	RISC-V: Fix riscv_isa_string memory size bug	Michael Clark	1	-6/+6
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2018-03-07	RISC-V Build Infrastructure	Michael Clark	1	-0/+1
2018-03-07	RISC-V Linux User Emulation	Michael Clark	1	-0/+13
2018-03-07	RISC-V Physical Memory Protection	Michael Clark	2	-0/+444
2018-03-07	RISC-V TCG Code Generation	Michael Clark	2	-0/+2342
2018-03-07	RISC-V GDB Stub	Michael Clark	1	-0/+62
2018-03-07	RISC-V FPU Support	Michael Clark	1	-0/+373
2018-03-07	RISC-V CPU Helpers	Michael Clark	3	-0/+1250
2018-03-07	RISC-V CPU Core Definition	Michael Clark	3	-0/+1139