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AgeCommit message (Expand)AuthorFilesLines
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing3-1/+18
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt3-0/+8
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt4-0/+9
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis3-5/+14
2019-06-25target/riscv: Remove user version informationAlistair Francis2-25/+9
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis1-0/+6
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis1-3/+5
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis2-2/+16
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis2-1/+2
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis2-14/+17
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary1-2/+1
2019-06-23RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary1-4/+5
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary2-1/+10
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary3-5/+13
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary1-3/+6
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary1-0/+1
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark3-0/+19
2019-06-23target/riscv: Fix PMP range boundary address bugDayeol Lee1-1/+1
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2-2/+79
2019-06-12Supply missing header guardsMarkus Armbruster3-0/+15
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster3-3/+0
2019-06-11qemu-common: Move qemu_isalnum() etc. to qemu/ctype.hMarkus Armbruster1-0/+1
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-3/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-2/+0
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson4-21/+13
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-1/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson2-17/+27
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens1-1/+3
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens1-2/+5
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson2-3/+14
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis1-0/+11
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis1-0/+18
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis1-3/+6
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis1-9/+8
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis1-3/+2
2019-05-24target/riscv: Improve the scause logicAlistair Francis1-1/+1
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2-8/+27
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis1-1/+1
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2-0/+16
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis2-0/+57
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson1-8/+8
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2-9/+24
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson6-151/+67
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson3-69/+29
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson3-53/+12
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2-170/+58
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