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2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra2-5/+2
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel4-14/+26
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak1-0/+1
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra1-8/+0
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li1-19/+25
2022-09-07target/riscv: Add Zihintpause supportDao Lu4-1/+25
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen2-2/+25
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen2-0/+14
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen2-0/+38
2022-09-07target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...Yueh-Ting (eop) Chen1-10/+16
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen2-0/+11
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen2-0/+8
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen2-0/+5
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen2-11/+29
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen6-2/+20
2022-09-07target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo1-1/+1
2022-09-07target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li1-13/+5
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li2-7/+7
2022-09-07target/riscv: Add check for csrs existed with U extensionWeiwei Li1-3/+21
2022-09-07target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li1-207/+234
2022-09-07target/riscv: H extension depends on I extensionWeiwei Li1-0/+6
2022-09-07target/riscv: Add check for supported privilege mode combinationsWeiwei Li1-0/+6
2022-09-07target/riscv: move zmmul out of the experimental propertiesWeiwei Li1-1/+2
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot2-5/+22
2022-09-07target/riscv: Force disable extensions if priv spec version does not matchAnup Patel1-56/+94
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel3-6/+296
2022-09-06target/riscv: Make translator stop before the end of a pageRichard Henderson1-4/+13
2022-09-06target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson1-1/+9
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
2022-09-01meson: remove dead codePaolo Bonzini1-2/+0
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt1-5/+0
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel2-70/+66
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2-168/+6
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel1-1/+1
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel1-4/+8
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis1-1/+1
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis1-1/+1
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra6-53/+213
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra3-152/+331
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra4-0/+32
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra3-36/+63
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra3-5/+5
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra1-0/+51
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra1-4/+7
2022-07-03target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre1-0/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson4-9/+17
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson1-9/+2
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson1-0/+2
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2