Age | Commit message (Expand) | Author | Files | Lines |
2022-09-07 | hw/intc: Move mtimer/mtimecmp to aclint | Atish Patra | 2 | -5/+2 |
2022-09-07 | target/riscv: Use official extension names for AIA CSRs | Anup Patel | 4 | -14/+26 |
2022-09-07 | target/riscv: Add xicondops in ISA entry | Rahul Pathak | 1 | -0/+1 |
2022-09-07 | target/riscv: Remove additional priv version check for mcountinhibit | Atish Patra | 1 | -8/+0 |
2022-09-07 | target/riscv: Fix priority of csr related check in riscv_csrrw_check | Weiwei Li | 1 | -19/+25 |
2022-09-07 | target/riscv: Add Zihintpause support | Dao Lu | 4 | -1/+25 |
2022-09-07 | target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti... | eopXD | 1 | -0/+1 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector permutation instructions | Yueh-Ting (eop) Chen | 2 | -2/+25 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector mask instructions | Yueh-Ting (eop) Chen | 2 | -0/+14 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector floating-point instructions | Yueh-Ting (eop) Chen | 2 | -0/+38 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct... | Yueh-Ting (eop) Chen | 1 | -10/+16 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector integer comparison instructions | Yueh-Ting (eop) Chen | 2 | -0/+11 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector integer shift instructions | Yueh-Ting (eop) Chen | 2 | -0/+8 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vx instructions | Yueh-Ting (eop) Chen | 2 | -0/+5 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector load / store instructions | Yueh-Ting (eop) Chen | 2 | -11/+29 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vv instructions | Yueh-Ting (eop) Chen | 6 | -2/+20 |
2022-09-07 | target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V | Alexey Baturo | 1 | -1/+1 |
2022-09-07 | target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c... | Weiwei Li | 1 | -13/+5 |
2022-09-07 | target/riscv: Fix checks in hmode/hmode32 | Weiwei Li | 2 | -7/+7 |
2022-09-07 | target/riscv: Add check for csrs existed with U extension | Weiwei Li | 1 | -3/+21 |
2022-09-07 | target/riscv: Fix checkpatch warning may triggered in csr_ops table | Weiwei Li | 1 | -207/+234 |
2022-09-07 | target/riscv: H extension depends on I extension | Weiwei Li | 1 | -0/+6 |
2022-09-07 | target/riscv: Add check for supported privilege mode combinations | Weiwei Li | 1 | -0/+6 |
2022-09-07 | target/riscv: move zmmul out of the experimental properties | Weiwei Li | 1 | -1/+2 |
2022-09-07 | target/riscv: fix shifts shamt value for rv128c | Frédéric Pétrot | 2 | -5/+22 |
2022-09-07 | target/riscv: Force disable extensions if priv spec version does not match | Anup Patel | 1 | -56/+94 |
2022-09-07 | target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() | Anup Patel | 3 | -6/+296 |
2022-09-06 | target/riscv: Make translator stop before the end of a page | Richard Henderson | 1 | -4/+13 |
2022-09-06 | target/riscv: Add MAX_INSN_LEN and insn_len | Richard Henderson | 1 | -1/+9 |
2022-09-06 | accel/tcg: Add pc and host_pc params to gen_intermediate_code | Richard Henderson | 1 | -2/+3 |
2022-09-01 | meson: remove dead code | Paolo Bonzini | 1 | -2/+0 |
2022-07-27 | RISC-V: Allow both Zmmul and M | Palmer Dabbelt | 1 | -5/+0 |
2022-07-03 | target/riscv: Update default priority table for local interrupts | Anup Patel | 2 | -70/+66 |
2022-07-03 | target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits | Anup Patel | 2 | -168/+6 |
2022-07-03 | target/riscv: Set minumum priv spec version for mcountinhibit | Anup Patel | 1 | -1/+1 |
2022-07-03 | target/riscv: Don't force update priv spec version to latest | Anup Patel | 1 | -4/+8 |
2022-07-03 | target/riscv: Ibex: Support priv version 1.11 | Alistair Francis | 1 | -1/+1 |
2022-07-03 | target/riscv: Fixup MSECCFG minimum priv check | Alistair Francis | 1 | -1/+1 |
2022-07-03 | target/riscv: Support mcycle/minstret write operation | Atish Patra | 6 | -53/+213 |
2022-07-03 | target/riscv: Add support for hpmcounters/hpmevents | Atish Patra | 3 | -152/+331 |
2022-07-03 | target/riscv: Implement mcountinhibit CSR | Atish Patra | 4 | -0/+32 |
2022-07-03 | target/riscv: pmu: Make number of counters configurable | Atish Patra | 3 | -36/+63 |
2022-07-03 | target/riscv: pmu: Rename the counters extension to pmu | Atish Patra | 3 | -5/+5 |
2022-07-03 | target/riscv: Implement PMU CSR predicate function for S-mode | Atish Patra | 1 | -0/+51 |
2022-07-03 | target/riscv: Fix PMU CSR predicate function | Atish Patra | 1 | -4/+7 |
2022-07-03 | target/riscv/pmp: guard against PMP ranges with a negative size | Nicolas Pitre | 1 | -0/+3 |
2022-07-03 | target/riscv: Minimize the calls to decode_save_opc | Richard Henderson | 4 | -9/+17 |
2022-07-03 | target/riscv: Remove generate_exception_mtval | Richard Henderson | 1 | -9/+2 |
2022-07-03 | target/riscv: Set env->bins in gen_exception_illegal | Richard Henderson | 1 | -0/+2 |
2022-07-03 | target/riscv: Remove condition guarding register zero for auipc and lui | Víctor Colombo | 1 | -6/+2 |