Age | Commit message (Expand) | Author | Files | Lines |
2022-07-27 | RISC-V: Allow both Zmmul and M | Palmer Dabbelt | 1 | -5/+0 |
2022-07-03 | target/riscv: Update default priority table for local interrupts | Anup Patel | 2 | -70/+66 |
2022-07-03 | target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits | Anup Patel | 2 | -168/+6 |
2022-07-03 | target/riscv: Set minumum priv spec version for mcountinhibit | Anup Patel | 1 | -1/+1 |
2022-07-03 | target/riscv: Don't force update priv spec version to latest | Anup Patel | 1 | -4/+8 |
2022-07-03 | target/riscv: Ibex: Support priv version 1.11 | Alistair Francis | 1 | -1/+1 |
2022-07-03 | target/riscv: Fixup MSECCFG minimum priv check | Alistair Francis | 1 | -1/+1 |
2022-07-03 | target/riscv: Support mcycle/minstret write operation | Atish Patra | 6 | -53/+213 |
2022-07-03 | target/riscv: Add support for hpmcounters/hpmevents | Atish Patra | 3 | -152/+331 |
2022-07-03 | target/riscv: Implement mcountinhibit CSR | Atish Patra | 4 | -0/+32 |
2022-07-03 | target/riscv: pmu: Make number of counters configurable | Atish Patra | 3 | -36/+63 |
2022-07-03 | target/riscv: pmu: Rename the counters extension to pmu | Atish Patra | 3 | -5/+5 |
2022-07-03 | target/riscv: Implement PMU CSR predicate function for S-mode | Atish Patra | 1 | -0/+51 |
2022-07-03 | target/riscv: Fix PMU CSR predicate function | Atish Patra | 1 | -4/+7 |
2022-07-03 | target/riscv/pmp: guard against PMP ranges with a negative size | Nicolas Pitre | 1 | -0/+3 |
2022-07-03 | target/riscv: Minimize the calls to decode_save_opc | Richard Henderson | 4 | -9/+17 |
2022-07-03 | target/riscv: Remove generate_exception_mtval | Richard Henderson | 1 | -9/+2 |
2022-07-03 | target/riscv: Set env->bins in gen_exception_illegal | Richard Henderson | 1 | -0/+2 |
2022-07-03 | target/riscv: Remove condition guarding register zero for auipc and lui | Víctor Colombo | 1 | -6/+2 |
2022-06-28 | semihosting: Split out common-semi-target.h | Richard Henderson | 1 | -0/+50 |
2022-06-28 | semihosting: Return void from do_common_semihosting | Richard Henderson | 1 | -1/+1 |
2022-06-10 | target/riscv: trans_rvv: Avoid assert for RV32 and e64 | Alistair Francis | 1 | -2/+10 |
2022-06-10 | target/riscv: Don't expose the CPU properties on names CPUs | Alistair Francis | 1 | -11/+46 |
2022-06-10 | target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti... | eopXD | 1 | -0/+2 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector permutation instructions | eopXD | 2 | -2/+45 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector mask instructions | eopXD | 2 | -0/+36 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector reduction instructions | eopXD | 1 | -0/+20 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector floating-point instructions | eopXD | 2 | -196/+261 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct... | eopXD | 1 | -106/+114 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer merge and move instru... | eopXD | 2 | -4/+28 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer comparison instructions | eopXD | 1 | -0/+18 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer shift instructions | eopXD | 2 | -1/+13 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions | eopXD | 3 | -142/+190 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector load / store instructions | eopXD | 3 | -0/+68 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vv instructions | eopXD | 6 | -132/+178 |
2022-06-10 | target/riscv: rvv: Early exit when vstart >= vl | eopXD | 1 | -0/+27 |
2022-06-10 | target/riscv: rvv: Rename ambiguous esz | eopXD | 1 | -38/+38 |
2022-06-10 | target/riscv: rvv: Prune redundant access_type parameter passed | eopXD | 1 | -19/+16 |
2022-06-10 | target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed | eopXD | 1 | -567/+565 |
2022-06-10 | target/riscv/debug.c: keep experimental rv128 support working | Frédéric Pétrot | 1 | -0/+2 |
2022-06-10 | target/riscv: Wake on VS-level external interrupts | Andrew Bresticker | 3 | -2/+3 |
2022-06-10 | target/riscv: add support for zmmul extension v0.1 | Weiwei Li | 3 | -6/+20 |
2022-05-24 | target/riscv: add zicsr/zifencei to isa_string | Hongren (Zenithal) Zheng | 1 | -0/+2 |
2022-05-24 | target/riscv: Set [m|s]tval for both illegal and virtual instruction traps | Anup Patel | 4 | -5/+23 |
2022-05-24 | target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode | Anup Patel | 1 | -2/+1 |
2022-05-24 | target/riscv: Fix csr number based privilege checking | Anup Patel | 1 | -2/+6 |
2022-05-24 | target/riscv: Fix typo of mimpid cpu option | Frank Chang | 3 | -7/+7 |
2022-05-24 | target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize | Weiwei Li | 1 | -12/+12 |
2022-05-24 | target/riscv: Move/refactor ISA extension checks | Tsukasa OI | 1 | -15/+16 |
2022-05-24 | target/riscv: FP extension requirements | Tsukasa OI | 1 | -0/+25 |