aboutsummaryrefslogtreecommitdiff
path: root/target/riscv
AgeCommit message (Expand)AuthorFilesLines
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng1-1/+1
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang2-0/+26
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2-0/+5
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng3-0/+35
2021-06-08target/riscv: rvb: address calculationKito Cheng3-0/+62
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang5-0/+64
2021-06-08target/riscv: rvb: generalized reverseFrank Chang6-0/+132
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng3-0/+81
2021-06-08target/riscv: rvb: shift onesKito Cheng3-0/+74
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang3-0/+175
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2-50/+43
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng2-0/+15
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng2-0/+28
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng3-0/+78
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng2-0/+21
2021-06-08target/riscv: rvb: count bits setFrank Chang3-0/+21
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng4-1/+93
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
2021-06-08target/riscv/pmp: Add assert for ePMP operationsAlistair Francis1-0/+4
2021-06-08target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du1-2/+5
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2-4/+2
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-06-08target/riscv: fix wfi exception behaviorJose Martins2-3/+9
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé1-2/+2
2021-05-26cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+8
2021-05-26cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé1-2/+1
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis5-72/+39
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis14-150/+166
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis4-28/+56
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis3-14/+27
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2-20/+15
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2-7/+8
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2-7/+5
2021-05-11target/riscv: fix a typo with interrupt namesEmmanuel Blot1-1/+1
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang1-2/+4
2021-05-11target/riscv: Add ePMP support for the Ibex CPUAlistair Francis1-0/+1
2021-05-11target/riscv/pmp: Remove outdated commentAlistair Francis1-4/+0
2021-05-11target/riscv: Add a config option for ePMPHou Weiying2-0/+11
2021-05-11target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying1-8/+146
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying5-0/+76
2021-05-11target/riscv: Add the ePMP featureAlistair Francis1-0/+1
generated by cgit v1.1 at 2024-12-27 11:04:12 +0000