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Author
Files
Lines
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
1
-7
/
+16
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
2
-2
/
+2
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move synchronize_from_tb() to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
target/riscv: remove CONFIG_TCG, as it is always TCG
Claudio Fontana
1
-2
/
+1
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
1
-1
/
+1
2021-01-18
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...
Peter Maydell
4
-1
/
+58
2021-01-18
riscv: Add semihosting support
Keith Packard
4
-1
/
+58
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
3
-264
/
+58
2021-01-16
target/riscv: Add CSR name in the CSR function table
Bin Meng
2
-84
/
+249
2021-01-16
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Bin Meng
2
-9
/
+9
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
3
-2
/
+8
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
1
-0
/
+13
2021-01-07
tcg: Make tb arg to synchronize_from_tb const
Richard Henderson
1
-1
/
+2
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
1
-9
/
+16
2020-12-17
target/riscv: csr: Remove compile time XLEN checks
Alistair Francis
2
-88
/
+92
2020-12-17
target/riscv: cpu_helper: Remove compile time XLEN checks
Alistair Francis
1
-5
/
+7
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
1
-9
/
+10
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
1
-10
/
+23
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
2
-0
/
+11
2020-12-17
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
2
-24
/
+8
2020-12-17
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Alistair Francis
1
-0
/
+6
2020-12-17
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alex Richardson
1
-2
/
+2
2020-12-17
target/riscv: Fix the bug of HLVX/HLV/HSV
Yifei Jiang
1
-1
/
+2
2020-11-13
hmp: Pass monitor to mon_get_cpu_env()
Kevin Wolf
1
-1
/
+1
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
3
-42
/
+17
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
5
-166
/
+59
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
4
-51
/
+25
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
1
-13
/
+17
2020-11-09
target/riscv: Add a virtualised MMU Mode
Alistair Francis
3
-3
/
+14
2020-11-03
target/riscv/csr.c : add space before the open parenthesis '('
Xinhao Zhang
1
-1
/
+1
2020-11-03
target/riscv: Add V extension state description
Yifei Jiang
1
-0
/
+25
2020-11-03
target/riscv: Add H extension state description
Yifei Jiang
1
-0
/
+47
2020-11-03
target/riscv: Add PMP state description
Yifei Jiang
3
-11
/
+70
2020-11-03
target/riscv: Add basic vmstate description of CPU
Yifei Jiang
4
-8
/
+81
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
6
-74
/
+41
2020-10-22
target/riscv: raise exception to HS-mode at get_physical_address
Yifei Jiang
2
-12
/
+34
2020-10-22
target/riscv: Fix implementation of HLVX.WU instruction
Georg Kotheimer
1
-3
/
+3
2020-10-22
target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt
Georg Kotheimer
1
-1
/
+3
2020-10-22
target/riscv: Fix update of hstatus.SPVP
Georg Kotheimer
1
-1
/
+1
2020-10-22
riscv: Convert interrupt logs to use qemu_log_mask()
Alistair Francis
2
-2
/
+7
2020-10-05
icount: rename functions to be consistent with the module name
Claudio Fontana
1
-2
/
+2
2020-10-05
cpu-timers, icount: new modules
Claudio Fontana
1
-2
/
+2
2020-09-23
qemu/atomic.h: rename atomic_ to qatomic_
Stefan Hajnoczi
1
-1
/
+1
2020-09-18
qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
Eduardo Habkost
1
-1
/
+1
2020-09-18
target/riscv: Set instance_align on RISCVCPU TypeInfo
Richard Henderson
1
-0
/
+1
2020-09-13
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...
Peter Maydell
4
-12
/
+27
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