riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-22	target/riscv: update mstatus.SD when FS is set dirty	ShihPo Hung	2	-3/+2
2020-06-22	target/riscv: fsd/fsw doesn't dirty FP state	ShihPo Hung	2	-2/+0
2020-06-22	target/riscv: Fix tb->flags FS status	ShihPo Hung	1	-4/+1
2020-06-22	riscv: Set xPIE to 1 after xRET	Yiting Wang	1	-2/+2
2019-11-14	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis	4	-43/+21
2019-11-14	remove unnecessary ifdef TARGET_RISCV64	hiroyuki.obinata	1	-3/+1
2019-10-30	Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...	Peter Maydell	1	-1/+1
2019-10-28	target/riscv: PMP violation due to wrong size parameter	Dayeol Lee	1	-1/+12
2019-10-28	target/riscv: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/riscv: Make the priv register writable by GDB	Jonathan Behrens	1	-0/+9
2019-10-28	target/riscv: Expose "priv" register for GDB for reads	Jonathan Behrens	1	-0/+23
2019-10-28	target/riscv: Tell gdbstub the correct number of CSRs	Jonathan Behrens	1	-2/+2
2019-10-28	linux-user/riscv: Propagate fault address	Giuseppe Musacchio	1	-1/+4
2019-10-28	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt	3	-7/+13
2019-10-28	RISC-V: Handle bus errors in the page table walker	Palmer Dabbelt	1	-3/+9
2019-10-28	riscv: Skip checking CSR privilege level in debugger mode	Bin Meng	1	-1/+4
2019-09-17	gdbstub: riscv: fix the fflags registers	KONRAD Frederic	1	-2/+4
2019-09-17	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point	Alistair Francis	1	-1/+1
2019-09-17	target/riscv: Fix mstatus dirty mask	Alistair Francis	1	-1/+1
2019-09-17	target/riscv: Use both register name and ABI name	Atish Patra	1	-8/+11
2019-09-17	riscv: hmp: Add a command to show virtual memory mappings	Bin Meng	2	-0/+233
2019-09-17	riscv: rv32: Root page table address can be larger than 32-bit	Bin Meng	1	-5/+5
2019-09-17	target/riscv: Update the Hypervisor CSRs to v0.4	Alistair Francis	1	-17/+18
2019-09-17	target/riscv: Create function to test if FP is enabled	Alistair Francis	3	-10/+26
2019-09-17	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	Philippe Mathieu-Daudé	2	-21/+16
2019-09-17	target/riscv/pmp: Restrict priviledged PMP to system-mode emulation	Philippe Mathieu-Daudé	2	-5/+2
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen	2	-6/+6
2019-08-22	Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...	Peter Maydell	1	-1/+1
2019-08-21	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster	1	-1/+1
2019-08-20	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk	1	-1/+0
2019-08-19	Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into staging	Peter Maydell	1	-18/+1
2019-08-19	target/riscv: Remove redundant declaration pragmas	Richard Henderson	1	-18/+1
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée	3	-1/+3
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing	3	-1/+18
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt	3	-0/+8
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt	4	-0/+9
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis	3	-5/+14
2019-06-25	target/riscv: Remove user version information	Alistair Francis	2	-25/+9
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis	1	-0/+6
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis	1	-3/+5
2019-06-25	target/riscv: Add the mcountinhibit CSR	Alistair Francis	2	-2/+16
2019-06-24	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis	2	-1/+2
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis	2	-14/+17
2019-06-23	RISC-V: Fix a PMP check with the correct access size	Hesham Almatary	1	-2/+1
2019-06-23	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	Hesham Almatary	1	-4/+5
2019-06-23	RISC-V: Check PMP during Page Table Walks	Hesham Almatary	2	-1/+10
2019-06-23	RISC-V: Check for the effective memory privilege mode during PMP checks	Hesham Almatary	3	-5/+13
2019-06-23	RISC-V: Raise access fault exceptions on PMP violations	Hesham Almatary	1	-3/+6
2019-06-23	RISC-V: Only Check PMP if MMU translation succeeds	Hesham Almatary	1	-0/+1
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark	3	-0/+19