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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+11
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-0/+2
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-10/+0
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson1-0/+18
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson1-0/+11
2020-08-21meson: targetPaolo Bonzini1-2/+2
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-10/+10
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei1-0/+7
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei1-2/+15
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei1-1/+2
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis1-0/+1
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-1/+1
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis1-0/+8
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée1-19/+21
2020-01-24Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell1-1/+1
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-11-14remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata1-3/+1
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-08-19target/riscv: Remove redundant declaration pragmasRichard Henderson1-18/+1
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+3
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson1-2/+17
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson1-1/+0
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson1-0/+6
2019-05-24target/riscv: Use --static-decode for decodetreeRichard Henderson1-3/+0
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson1-0/+18
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau1-5/+25
2019-05-06decodetree: Add DisasContext argument to !function expandersRichard Henderson1-2/+2
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt1-0/+21
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann1-20/+1
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann1-34/+0
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann1-2/+2
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann1-187/+133
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann1-41/+18
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann1-15/+25
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann1-80/+27
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann1-3/+5
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann1-2/+4
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann1-47/+0
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann1-38/+0
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann1-81/+2
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann1-117/+1
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann1-37/+16
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann1-56/+1
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann1-600/+1
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann1-0/+1
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann1-0/+1
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