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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-4/+13
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li1-0/+1
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-0/+7
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-4/+6
2022-03-03target/riscv: add support for zdinxWeiwei Li1-0/+52
2022-03-03target/riscv: add support for zfinxWeiwei Li1-1/+92
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-0/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+12
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich1-5/+27
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich1-14/+0
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich1-0/+2
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-4/+8
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei1-13/+12
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei1-24/+8
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei1-4/+21
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei1-3/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-0/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-0/+2
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+3
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis1-0/+2
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot1-12/+51
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot1-15/+43
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot1-0/+21
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot1-2/+19
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot1-0/+41
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-1/+4
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot1-0/+27
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot1-4/+16
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-1/+5
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang1-0/+7
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang1-2/+0
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang1-0/+40
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang1-0/+2
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng1-0/+10
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng1-0/+8
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-2/+37
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo1-0/+8
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-3/+2
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson1-0/+31
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson1-0/+16
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson1-0/+16
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson1-25/+44
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-1/+1
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-4/+6
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang1-1/+1
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson1-26/+1
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