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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot1-12/+51
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot1-15/+43
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot1-0/+21
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot1-2/+19
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot1-0/+41
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-1/+4
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot1-0/+27
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot1-4/+16
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-1/+5
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang1-0/+7
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang1-2/+0
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang1-0/+40
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang1-0/+2
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng1-0/+10
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng1-0/+8
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-2/+37
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo1-0/+8
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-3/+2
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson1-0/+31
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson1-0/+16
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson1-0/+16
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson1-25/+44
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-1/+1
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-4/+6
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang1-1/+1
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson1-26/+1
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang1-13/+17
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich1-0/+6
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-2/+3
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson1-8/+5
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson1-62/+48
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson1-8/+6
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson1-233/+0
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson1-127/+0
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson1-42/+0
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson1-50/+19
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson1-16/+81
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson1-29/+29
2021-09-01target/riscv: Clean up division helpersRichard Henderson1-83/+91
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson1-26/+10
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-17/+0
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson1-19/+1
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+6
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+32
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+6
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+28
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