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path: root/target/riscv/translate.c
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2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-2/+37
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo1-0/+8
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-3/+2
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson1-0/+31
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson1-0/+16
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson1-0/+16
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson1-25/+44
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-1/+1
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-4/+6
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang1-1/+1
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson1-26/+1
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang1-13/+17
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich1-0/+6
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-2/+3
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson1-8/+5
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson1-62/+48
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson1-8/+6
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson1-233/+0
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson1-127/+0
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson1-42/+0
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson1-50/+19
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson1-16/+81
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson1-29/+29
2021-09-01target/riscv: Clean up division helpersRichard Henderson1-83/+91
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson1-26/+10
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-17/+0
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson1-19/+1
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+6
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+32
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+6
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+28
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+36
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+14
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+61
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang1-0/+39
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+40
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+6
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+38
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-3/+6
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-2/+17
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-2/+2
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer1-178/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+11
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-0/+2
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-10/+0
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson1-0/+18
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson1-0/+11
generated by cgit v1.1 at 2025-02-02 17:09:56 +0000