riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-09-07	target/riscv: Add stimecmp support	Atish Patra	1	-1/+2
2022-09-01	meson: remove dead code	Paolo Bonzini	1	-2/+0
2022-07-03	target/riscv: Support mcycle/minstret write operation	Atish Patra	1	-1/+2
2022-04-29	target/riscv: rvk: add support for zknd/zkne extension in RV32	Weiwei Li	1	-1/+2
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng	1	-0/+1
2022-02-16	target/riscv: Add XVentanaCondOps custom extension	Philipp Tomsich	1	-0/+1
2022-01-21	target/riscv: Support start kernel directly by KVM	Yifei Jiang	1	-1/+1
2022-01-21	target/riscv: Add target/riscv/kvm.c to place the public kvm interface	Yifei Jiang	1	-0/+1
2022-01-08	target/riscv: support for 128-bit M extension	Frédéric Pétrot	1	-0/+1
2021-06-08	target/riscv: rvb: generalized reverse	Frank Chang	1	-0/+1
2021-05-11	target/riscv: Consolidate RV32/64 16-bit instructions	Alistair Francis	1	-8/+3
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	1	-1/+1
2021-03-04	target-riscv: support QMP dump-guest-memory	Yifei Jiang	1	-0/+1
2020-11-03	target/riscv: Add basic vmstate description of CPU	Yifei Jiang	1	-1/+2
2020-08-21	meson: target	Paolo Bonzini	1	-0/+34