riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-03-03	target/riscv: add support for zhinx/zhinxmin	Weiwei Li	1	-3/+13
2022-03-03	target/riscv: add support for zfinx	Weiwei Li	1	-3/+13
2021-12-20	target/riscv: add "set round to odd" rounding mode helper function	Frank Chang	1	-0/+1
2021-12-20	target/riscv: introduce floating-point rounding mode enum	Frank Chang	1	-0/+9
2021-12-20	target/riscv: rvv-1.0: floating-point scalar move instructions	Frank Chang	1	-5/+0
2021-12-20	target/riscv: rvv-1.0: remove MLEN calculations	Frank Chang	1	-5/+4
2021-12-20	target/riscv: zfh: half-precision computational	Kito Cheng	1	-0/+16
2020-11-03	target/riscv: Add basic vmstate description of CPU	Yifei Jiang	1	-0/+4
2020-08-21	target/riscv: Check nanboxed inputs to fp helpers	Richard Henderson	1	-0/+11
2020-08-21	target/riscv: Generate nanboxed results from fp helpers	Richard Henderson	1	-0/+5
2020-07-02	target/riscv: integer scalar move instruction	LIU Zhiwei	1	-0/+6
2020-07-02	target/riscv: vector floating-point classify instructions	LIU Zhiwei	1	-0/+5
2020-07-02	target/riscv: add vector amo operations	LIU Zhiwei	1	-0/+1
2020-07-02	target/riscv: add vector stride load and store instructions	LIU Zhiwei	1	-0/+5
2020-07-02	target/riscv: add an internals.h header	LIU Zhiwei	1	-0/+24