Age | Commit message (Expand) | Author | Files | Lines |
2019-05-24 | target/riscv: Split gen_arith_imm into functional and temp | Richard Henderson | 1 | -7/+7 |
2019-05-24 | target/riscv: Split RVC32 and RVC64 insns into separate files | Richard Henderson | 1 | -115/+0 |
2019-05-24 | target/riscv: Use pattern groups in insn16.decode | Richard Henderson | 2 | -63/+6 |
2019-05-24 | target/riscv: Merge argument decode for RVC shifti | Richard Henderson | 1 | -47/+0 |
2019-05-24 | target/riscv: Merge argument sets for insn32 and insn16 | Richard Henderson | 1 | -133/+11 |
2019-05-24 | RISC-V: fix single stepping over ret and other branching instructions | Fabien Chouteau | 2 | -7/+7 |
2019-05-06 | decodetree: Add DisasContext argument to !function expanders | Richard Henderson | 1 | -5/+5 |
2019-03-26 | target/riscv: Fix wrong expanding for c.fswsp | Kito Cheng | 1 | -1/+1 |
2019-03-22 | target/riscv: Zero extend the inputs of divuw and remuw | Palmer Dabbelt | 1 | -2/+2 |
2019-03-17 | target/riscv: Fix manually parsed 16 bit insn | Bastian Koppelmann | 1 | -5/+25 |
2019-03-13 | target/riscv: Rename trans_arith to gen_arith | Bastian Koppelmann | 2 | -16/+16 |
2019-03-13 | target/riscv: Remove manual decoding of RV32/64M insn | Bastian Koppelmann | 1 | -24/+31 |
2019-03-13 | target/riscv: Remove shift and slt insn manual decoding | Bastian Koppelmann | 1 | -30/+63 |
2019-03-13 | target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists | Bastian Koppelmann | 1 | -14/+7 |
2019-03-13 | target/riscv: Move gen_arith_imm() decoding into trans_* functions | Bastian Koppelmann | 1 | -19/+79 |
2019-03-13 | target/riscv: Remove manual decoding from gen_store() | Bastian Koppelmann | 1 | -8/+19 |
2019-03-13 | target/riscv: Remove manual decoding from gen_load() | Bastian Koppelmann | 1 | -14/+21 |
2019-03-13 | target/riscv: Remove manual decoding from gen_branch() | Bastian Koppelmann | 1 | -13/+33 |
2019-03-13 | target/riscv: Remove gen_jalr() | Bastian Koppelmann | 1 | -1/+27 |
2019-03-13 | target/riscv: Convert quadrant 2 of RVXC insns to decodetree | Bastian Koppelmann | 1 | -0/+101 |
2019-03-13 | target/riscv: Convert quadrant 1 of RVXC insns to decodetree | Bastian Koppelmann | 1 | -0/+151 |
2019-03-13 | target/riscv: Convert quadrant 0 of RVXC insns to decodetree | Bastian Koppelmann | 1 | -0/+75 |
2019-03-13 | target/riscv: Convert RV priv insns to decodetree | Bastian Koppelmann | 1 | -0/+110 |
2019-03-13 | target/riscv: Convert RV64D insns to decodetree | Bastian Koppelmann | 1 | -0/+82 |
2019-03-13 | target/riscv: Convert RV32D insns to decodetree | Bastian Koppelmann | 1 | -0/+360 |
2019-03-13 | target/riscv: Convert RV64F insns to decodetree | Bastian Koppelmann | 1 | -0/+60 |
2019-03-13 | target/riscv: Convert RV32F insns to decodetree | Bastian Koppelmann | 1 | -0/+379 |
2019-03-13 | target/riscv: Convert RV64A insns to decodetree | Bastian Koppelmann | 1 | -0/+58 |
2019-03-13 | target/riscv: Convert RV32A insns to decodetree | Bastian Koppelmann | 1 | -0/+160 |
2019-03-13 | target/riscv: Convert RVXM insns to decodetree | Bastian Koppelmann | 1 | -0/+113 |
2019-03-13 | target/riscv: Convert RVXI csr insns to decodetree | Bastian Koppelmann | 1 | -0/+79 |
2019-03-13 | target/riscv: Convert RVXI fence insns to decodetree | Bastian Koppelmann | 1 | -0/+19 |
2019-03-13 | target/riscv: Convert RVXI arithmetic insns to decodetree | Bastian Koppelmann | 1 | -0/+168 |
2019-03-13 | target/riscv: Convert RV64I load/store insns to decodetree | Bastian Koppelmann | 1 | -0/+20 |
2019-03-13 | target/riscv: Convert RV32I load/store insns to decodetree | Bastian Koppelmann | 1 | -0/+48 |
2019-03-13 | target/riscv: Convert RVXI branch insns to decodetree | Bastian Koppelmann | 1 | -0/+49 |
2019-03-13 | target/riscv: Activate decodetree and implemnt LUI & AUIPC | Bastian Koppelmann | 1 | -0/+35 |