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path: root/target/riscv/insn_trans
AgeCommit message (Expand)AuthorFilesLines
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2-6/+6
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk1-1/+0
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing1-1/+7
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+4
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis1-1/+1
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson1-7/+7
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson1-115/+0
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson2-63/+6
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson1-47/+0
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson1-133/+11
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2-7/+7
2019-05-06decodetree: Add DisasContext argument to !function expandersRichard Henderson1-5/+5
2019-03-26target/riscv: Fix wrong expanding for c.fswspKito Cheng1-1/+1
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt1-2/+2
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann1-5/+25
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2-16/+16
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann1-24/+31
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann1-30/+63
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann1-14/+7
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann1-19/+79
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann1-8/+19
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann1-14/+21
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann1-13/+33
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann1-1/+27
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann1-0/+101
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann1-0/+151
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann1-0/+75
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann1-0/+110
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann1-0/+82
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann1-0/+360
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann1-0/+60
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann1-0/+379
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann1-0/+58
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann1-0/+160
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann1-0/+113
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann1-0/+79
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann1-0/+19
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann1-0/+168
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann1-0/+20
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann1-0/+48
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann1-0/+49
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann1-0/+35
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