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AgeCommit message (Expand)AuthorFilesLines
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-13/+169
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot3-37/+168
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2-29/+217
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot1-4/+4
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot1-6/+94
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot1-17/+17
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2-9/+9
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot4-17/+17
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang1-8/+24
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang1-9/+25
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang1-4/+8
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang1-6/+11
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang1-0/+40
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang1-0/+27
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang1-0/+22
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-27/+48
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang1-9/+50
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang1-8/+47
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang1-32/+52
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang1-9/+9
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang1-23/+0
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang1-2/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang1-9/+0
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang1-1/+8
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang1-3/+9
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang1-6/+6
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang1-0/+16
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang1-1/+2
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang1-21/+21
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang1-1/+4
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang1-0/+80
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang1-0/+25
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang1-19/+19
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang1-8/+35
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang1-3/+24
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang1-10/+22
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang1-2/+8
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang1-1/+4
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