| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-10-28 | target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr... | Alexey Baturo | 4 | -0/+9 |
| 2021-10-22 | target/riscv: Use gen_shift*_per_ol for RVB, RVI | Richard Henderson | 2 | -52/+66 |
| 2021-10-22 | target/riscv: Use gen_unary_per_ol for RVB | Richard Henderson | 1 | -17/+16 |
| 2021-10-22 | target/riscv: Adjust trans_rev8_32 for riscv64 | Richard Henderson | 1 | -1/+6 |
| 2021-10-22 | target/riscv: Use gen_arith_per_ol for RVM | Richard Henderson | 1 | -3/+23 |
| 2021-10-22 | target/riscv: Replace DisasContext.w with DisasContext.ol | Richard Henderson | 3 | -18/+18 |
| 2021-10-22 | target/riscv: Properly check SEW in amo_op | Richard Henderson | 1 | -12/+14 |
| 2021-10-22 | target/riscv: Use REQUIRE_64BIT in amo_check64 | Richard Henderson | 1 | -1/+2 |
| 2021-10-22 | target/riscv: Fix orc.b implementation | Philipp Tomsich | 1 | -5/+8 |
| 2021-10-22 | target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v | Frank Chang | 1 | -1/+2 |
| 2021-10-15 | target/riscv: Remove exit_tb and lookup_and_goto_ptr | Richard Henderson | 3 | -8/+6 |
| 2021-10-15 | target/riscv: Remove dead code after exception | Richard Henderson | 1 | -5/+1 |
| 2021-10-07 | target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh | Philipp Tomsich | 1 | -72/+14 |
| 2021-10-07 | target/riscv: Add rev8 instruction, removing grev/grevi | Philipp Tomsich | 1 | -32/+8 |
| 2021-10-07 | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci | Philipp Tomsich | 1 | -22/+17 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbb-extension | Philipp Tomsich | 1 | -22/+29 |
| 2021-10-07 | target/riscv: Add instructions of the Zbc-extension | Philipp Tomsich | 1 | -1/+31 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbs-extension | Philipp Tomsich | 1 | -10/+15 |
| 2021-10-07 | target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) | Philipp Tomsich | 1 | -70/+0 |
| 2021-10-07 | target/riscv: Remove the W-form instructions from Zbs | Philipp Tomsich | 1 | -56/+0 |
| 2021-10-07 | target/riscv: Reassign instructions to the Zba-extension | Philipp Tomsich | 1 | -5/+11 |
| 2021-10-07 | target/riscv: clwz must ignore high bits (use shift-left & changed logic) | Philipp Tomsich | 1 | -3/+5 |
| 2021-10-07 | target/riscv: fix clzw implementation to operate on arg1 | Philipp Tomsich | 1 | -1/+1 |
| 2021-10-07 | target/riscv: Introduce temporary in gen_add_uw() | Philipp Tomsich | 1 | -2/+4 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson | 1 | -53/+21 |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson | 1 | -210/+56 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson | 1 | -65/+60 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson | 1 | -76/+70 |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson | 1 | -13/+6 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson | 1 | -28/+19 |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson | 1 | -52/+122 |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson | 1 | -18/+20 |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson | 1 | -15/+10 |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson | 1 | -2/+12 |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson | 2 | -140/+77 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson | 1 | -15/+9 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson | 1 | -0/+234 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson | 1 | -0/+127 |
| 2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson | 1 | -22/+18 |
| 2021-09-01 | target/riscv: Remove gen_arith_div* | Richard Henderson | 1 | -8/+8 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_arith* | Richard Henderson | 3 | -40/+45 |
| 2021-09-01 | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr | Richard Henderson | 8 | -115/+115 |
| 2021-09-01 | target/riscv: Use tcg_constant_* | Richard Henderson | 2 | -44/+24 |
| 2021-06-08 | target/riscv: rvb: add/shift with prefix zero-extend | Kito Cheng | 1 | -0/+26 |
| 2021-06-08 | target/riscv: rvb: address calculation | Kito Cheng | 1 | -0/+24 |
| 2021-06-08 | target/riscv: rvb: generalized or-combine | Frank Chang | 1 | -0/+26 |
| 2021-06-08 | target/riscv: rvb: generalized reverse | Frank Chang | 1 | -0/+31 |
| 2021-06-08 | target/riscv: rvb: rotate (left/right) | Kito Cheng | 1 | -0/+39 |
| 2021-06-08 | target/riscv: rvb: shift ones | Kito Cheng | 1 | -0/+52 |
| 2021-06-08 | target/riscv: rvb: single-bit instructions | Frank Chang | 1 | -0/+97 |
