riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-10-07	target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh	Philipp Tomsich	1	-72/+14
2021-10-07	target/riscv: Add rev8 instruction, removing grev/grevi	Philipp Tomsich	1	-32/+8
2021-10-07	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	Philipp Tomsich	1	-22/+17
2021-10-07	target/riscv: Reassign instructions to the Zbb-extension	Philipp Tomsich	1	-22/+29
2021-10-07	target/riscv: Add instructions of the Zbc-extension	Philipp Tomsich	1	-1/+31
2021-10-07	target/riscv: Reassign instructions to the Zbs-extension	Philipp Tomsich	1	-10/+15
2021-10-07	target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)	Philipp Tomsich	1	-70/+0
2021-10-07	target/riscv: Remove the W-form instructions from Zbs	Philipp Tomsich	1	-56/+0
2021-10-07	target/riscv: Reassign instructions to the Zba-extension	Philipp Tomsich	1	-5/+11
2021-10-07	target/riscv: clwz must ignore high bits (use shift-left & changed logic)	Philipp Tomsich	1	-3/+5
2021-10-07	target/riscv: fix clzw implementation to operate on arg1	Philipp Tomsich	1	-1/+1
2021-10-07	target/riscv: Introduce temporary in gen_add_uw()	Philipp Tomsich	1	-2/+4
2021-09-01	target/riscv: Use gen_shift_imm_fn for slli_uw	Richard Henderson	1	-13/+6
2021-09-01	target/riscv: Use DisasExtend in shift operations	Richard Henderson	1	-70/+59
2021-09-01	target/riscv: Add DisasExtend to gen_unary	Richard Henderson	1	-15/+9
2021-09-01	target/riscv: Move gen_* helpers for RVB	Richard Henderson	1	-0/+234
2021-09-01	target/riscv: Add DisasExtend to gen_arith*	Richard Henderson	1	-15/+15
2021-09-01	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	Richard Henderson	1	-2/+2
2021-06-08	target/riscv: rvb: add/shift with prefix zero-extend	Kito Cheng	1	-0/+26
2021-06-08	target/riscv: rvb: address calculation	Kito Cheng	1	-0/+24
2021-06-08	target/riscv: rvb: generalized or-combine	Frank Chang	1	-0/+26
2021-06-08	target/riscv: rvb: generalized reverse	Frank Chang	1	-0/+31
2021-06-08	target/riscv: rvb: rotate (left/right)	Kito Cheng	1	-0/+39
2021-06-08	target/riscv: rvb: shift ones	Kito Cheng	1	-0/+52
2021-06-08	target/riscv: rvb: single-bit instructions	Frank Chang	1	-0/+97
2021-06-08	target/riscv: rvb: sign-extend instructions	Kito Cheng	1	-0/+12
2021-06-08	target/riscv: rvb: min/max instructions	Kito Cheng	1	-0/+24
2021-06-08	target/riscv: rvb: pack two words into one register	Kito Cheng	1	-0/+32
2021-06-08	target/riscv: rvb: logic-with-negate	Kito Cheng	1	-0/+18
2021-06-08	target/riscv: rvb: count bits set	Frank Chang	1	-0/+13
2021-06-08	target/riscv: rvb: count leading/trailing zeros	Kito Cheng	1	-0/+44