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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)AuthorFilesLines
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei1-0/+9
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei1-0/+11
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei1-0/+16
2020-07-02target/riscv: vector single-width integer add and subtractLIU Zhiwei1-0/+10
2020-07-02target/riscv: add vector amo operationsLIU Zhiwei1-0/+13
2020-07-02target/riscv: add fault-only-first unit stride loadLIU Zhiwei1-0/+7
2020-07-02target/riscv: add vector index load and store instructionsLIU Zhiwei1-0/+13
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei1-0/+32
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei1-0/+5
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis1-3/+5
2020-02-27target/riscv: Remove the hret instructionAlistair Francis1-1/+0
2020-02-27target/riscv: Add hfence instructionsAlistair Francis1-9/+14
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson1-3/+7
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann1-1/+2
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann1-1/+2
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann1-0/+15
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann1-0/+28
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann1-0/+35
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann1-0/+17
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann1-0/+10
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann1-0/+8
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann1-0/+2
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann1-0/+25
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann1-0/+10
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann1-0/+19
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann1-0/+30
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