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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)AuthorFilesLines
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+3
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+6
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+4
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+4
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+6
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+8
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+17
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng1-0/+3
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng1-0/+4
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+6
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng1-0/+3
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+2
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-1/+10
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-1/+66
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+11
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei1-0/+3
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: integer extract instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+3
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei1-0/+12
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector floating-point square-root instructionLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei1-0/+16
2020-07-02target/riscv: vector widening floating-point multiplyLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector single-width scaling shift instructionsLIU Zhiwei1-0/+6
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