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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)AuthorFilesLines
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+11
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei1-0/+3
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: integer extract instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+3
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei1-0/+12
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector floating-point square-root instructionLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei1-0/+16
2020-07-02target/riscv: vector widening floating-point multiplyLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector single-width scaling shift instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector widening saturating scaled multiply-addLIU Zhiwei1-0/+7
2020-07-02target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width averaging add and subtractLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector single-width saturating add and subtractLIU Zhiwei1-0/+10
2020-07-02target/riscv: vector integer merge and move instructionsLIU Zhiwei1-0/+7
2020-07-02target/riscv: vector widening integer multiply-add instructionsLIU Zhiwei1-0/+7
2020-07-02target/riscv: vector single-width integer multiply-add instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector widening integer multiply instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector integer divide instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector single-width integer multiply instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector integer min/max instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei1-0/+20
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei1-0/+9
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei1-0/+9
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei1-0/+11
generated by cgit v1.1 at 2024-12-29 17:45:49 +0000