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path: root/target/riscv/helper.h
AgeCommit message (Expand)AuthorFilesLines
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li1-1/+1
2022-03-03target/riscv: add support for zfinxWeiwei Li1-1/+1
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei1-2/+2
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+3
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-0/+6
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-0/+5
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang1-10/+12
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang1-6/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang1-22/+0
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang1-0/+7
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang1-0/+16
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang1-0/+14
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang1-0/+21
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang1-22/+4
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang1-35/+32
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang1-105/+24
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang1-27/+0
2021-12-20target/riscv: zfh: half-precision floating-point classifyKito Cheng1-0/+1
2021-12-20target/riscv: zfh: half-precision floating-point compareKito Cheng1-0/+3
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng1-0/+12
2021-12-20target/riscv: zfh: half-precision computationalKito Cheng1-0/+13
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich1-2/+0
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich1-2/+0
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich1-0/+2
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson1-3/+3
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+2
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+4
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-10/+8
2020-12-17target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis1-16/+8
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis1-1/+2
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-2/+0
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-0/+1
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+3
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+9
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+17
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+5
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+4
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