Age | Commit message (Expand) | Author | Files | Lines |
2021-10-07 | target/riscv: Add rev8 instruction, removing grev/grevi | Philipp Tomsich | 1 | -2/+0 |
2021-10-07 | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci | Philipp Tomsich | 1 | -2/+0 |
2021-10-07 | target/riscv: Add instructions of the Zbc-extension | Philipp Tomsich | 1 | -0/+2 |
2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson | 1 | -3/+3 |
2021-06-08 | target/riscv: rvb: generalized or-combine | Frank Chang | 1 | -0/+2 |
2021-06-08 | target/riscv: rvb: generalized reverse | Frank Chang | 1 | -0/+4 |
2021-05-11 | target/riscv: Consolidate RV32/64 32-bit instructions | Alistair Francis | 1 | -10/+8 |
2020-12-17 | target/riscv: fpu_helper: Match function defs in HELPER macros | Alistair Francis | 1 | -16/+8 |
2020-11-09 | target/riscv: Split the Hypervisor execute load helpers | Alistair Francis | 1 | -1/+2 |
2020-11-09 | target/riscv: Remove the hyp load and store functions | Alistair Francis | 1 | -2/+0 |
2020-08-25 | target/riscv: Support the Virtual Instruction fault | Alistair Francis | 1 | -0/+1 |
2020-08-25 | target/riscv: Allow generating hlv/hlvx/hsv instructions | Alistair Francis | 1 | -0/+3 |
2020-07-02 | target/riscv: vector compress instruction | LIU Zhiwei | 1 | -0/+5 |
2020-07-02 | target/riscv: vector register gather instruction | LIU Zhiwei | 1 | -0/+9 |
2020-07-02 | target/riscv: vector slide instructions | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector element index instruction | LIU Zhiwei | 1 | -0/+5 |
2020-07-02 | target/riscv: vector iota instruction | LIU Zhiwei | 1 | -0/+5 |
2020-07-02 | target/riscv: set-X-first mask bit | LIU Zhiwei | 1 | -0/+4 |
2020-07-02 | target/riscv: vmfirst find-first-set mask bit | LIU Zhiwei | 1 | -0/+2 |
2020-07-02 | target/riscv: vector mask population count vmpopc | LIU Zhiwei | 1 | -0/+2 |
2020-07-02 | target/riscv: vector mask-register logical instructions | LIU Zhiwei | 1 | -0/+9 |
2020-07-02 | target/riscv: vector widening floating-point reduction instructions | LIU Zhiwei | 1 | -0/+3 |
2020-07-02 | target/riscv: vector single-width floating-point reduction instructions | LIU Zhiwei | 1 | -0/+10 |
2020-07-02 | target/riscv: vector wideing integer reduction instructions | LIU Zhiwei | 1 | -0/+7 |
2020-07-02 | target/riscv: vector single-width integer reduction instructions | LIU Zhiwei | 1 | -0/+33 |
2020-07-02 | target/riscv: narrowing floating-point/integer type-convert instructions | LIU Zhiwei | 1 | -0/+11 |
2020-07-02 | target/riscv: widening floating-point/integer type-convert instructions | LIU Zhiwei | 1 | -0/+11 |
2020-07-02 | target/riscv: vector floating-point/integer type-convert instructions | LIU Zhiwei | 1 | -0/+13 |
2020-07-02 | target/riscv: vector floating-point merge instructions | LIU Zhiwei | 1 | -0/+4 |
2020-07-02 | target/riscv: vector floating-point classify instructions | LIU Zhiwei | 1 | -0/+4 |
2020-07-02 | target/riscv: vector floating-point compare instructions | LIU Zhiwei | 1 | -0/+37 |
2020-07-02 | target/riscv: vector floating-point sign-injection instructions | LIU Zhiwei | 1 | -0/+19 |
2020-07-02 | target/riscv: vector floating-point min/max instructions | LIU Zhiwei | 1 | -0/+13 |
2020-07-02 | target/riscv: vector floating-point square-root instruction | LIU Zhiwei | 1 | -0/+4 |
2020-07-02 | target/riscv: vector widening floating-point fused multiply-add instructions | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector single-width floating-point fused multiply-add instructions | LIU Zhiwei | 1 | -0/+49 |
2020-07-02 | target/riscv: vector widening floating-point multiply | LIU Zhiwei | 1 | -0/+5 |
2020-07-02 | target/riscv: vector single-width floating-point multiply/divide instructions | LIU Zhiwei | 1 | -0/+16 |
2020-07-02 | target/riscv: vector widening floating-point add/subtract instructions | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector single-width floating-point add/subtract instructions | LIU Zhiwei | 1 | -0/+16 |
2020-07-02 | target/riscv: vector narrowing fixed-point clip instructions | LIU Zhiwei | 1 | -0/+13 |
2020-07-02 | target/riscv: vector single-width scaling shift instructions | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector widening saturating scaled multiply-add | LIU Zhiwei | 1 | -0/+22 |
2020-07-02 | target/riscv: vector single-width fractional multiply with rounding and satur... | LIU Zhiwei | 1 | -0/+9 |
2020-07-02 | target/riscv: vector single-width averaging add and subtract | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector single-width saturating add and subtract | LIU Zhiwei | 1 | -0/+33 |
2020-07-02 | target/riscv: vector integer merge and move instructions | LIU Zhiwei | 1 | -0/+17 |
2020-07-02 | target/riscv: vector widening integer multiply-add instructions | LIU Zhiwei | 1 | -0/+22 |
2020-07-02 | target/riscv: vector single-width integer multiply-add instructions | LIU Zhiwei | 1 | -0/+33 |
2020-07-02 | target/riscv: vector widening integer multiply instructions | LIU Zhiwei | 1 | -0/+19 |