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path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang1-1/+1
2022-09-27target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li1-4/+9
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra1-30/+60
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra1-101/+9
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-9/+157
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-3/+85
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+86
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-6/+18
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra1-8/+0
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li1-19/+25
2022-09-07target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li1-13/+5
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li1-7/+2
2022-09-07target/riscv: Add check for csrs existed with U extensionWeiwei Li1-3/+21
2022-09-07target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li1-207/+234
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel1-147/+3
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel1-1/+1
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis1-1/+1
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra1-43/+112
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra1-152/+317
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra1-0/+25
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra1-33/+61
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra1-2/+2
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra1-0/+51
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra1-4/+7
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel1-2/+6
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang1-4/+4
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid1-5/+5
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li1-0/+80
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang1-4/+34
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng1-0/+57
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis1-2/+6
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra1-0/+5
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra1-0/+107
2022-04-22target/riscv: Add support for mconfigptrAtish Patra1-0/+2
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra1-35/+68
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt1-6/+8
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé1-0/+1
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-5/+20
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé1-0/+1
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel1-0/+203
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel1-0/+177
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel1-0/+156
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel1-0/+23
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel1-1/+127
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-103/+457
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-13/+30
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel1-7/+11
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel1-1/+1
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei1-6/+22
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