Age | Commit message (Expand) | Author | Files | Lines |
2020-07-02 | target/riscv: support vector extension csr | LIU Zhiwei | 1 | -1/+74 |
2020-06-03 | target/riscv: Drop support for ISA spec version 1.09.1 | Alistair Francis | 1 | -113/+25 |
2020-02-27 | target/riscv: Emulate TIME CSRs for privileged mode | Anup Patel | 1 | -4/+82 |
2020-02-27 | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis | 1 | -0/+25 |
2020-02-27 | target/riscv: Extend the SIP CSR to support virtulisation | Alistair Francis | 1 | -1/+12 |
2020-02-27 | target/riscv: Extend the MIE CSR to support virtulisation | Alistair Francis | 1 | -4/+20 |
2020-02-27 | target/riscv: Set VS bits in mideleg for Hyp extension | Alistair Francis | 1 | -0/+3 |
2020-02-27 | target/riscv: Add Hypervisor machine CSRs accesses | Alistair Francis | 1 | -0/+27 |
2020-02-27 | target/riscv: Add Hypervisor virtual CSRs accesses | Alistair Francis | 1 | -0/+116 |
2020-02-27 | target/riscv: Add Hypervisor CSR access functions | Alistair Francis | 1 | -2/+134 |
2020-02-27 | target/riscv: Fix CSR perm checking for HS mode | Alistair Francis | 1 | -4/+14 |
2020-02-27 | target/riscv: Add support for the new execption numbers | Alistair Francis | 1 | -2/+5 |
2020-01-16 | target/riscv: update mstatus.SD when FS is set dirty | ShihPo Hung | 1 | -2/+1 |
2019-11-14 | target/riscv: Remove atomic accesses to MIP CSR | Alistair Francis | 1 | -1/+1 |
2019-10-28 | riscv: Skip checking CSR privilege level in debugger mode | Bin Meng | 1 | -1/+4 |
2019-09-17 | target/riscv: Fix mstatus dirty mask | Alistair Francis | 1 | -1/+1 |
2019-09-17 | target/riscv: Create function to test if FP is enabled | Alistair Francis | 1 | -9/+11 |
2019-06-25 | RISC-V: Add support for the Zicsr extension | Palmer Dabbelt | 1 | -0/+6 |
2019-06-25 | target/riscv: Add support for disabling/enabling Counters | Alistair Francis | 1 | -5/+12 |
2019-06-25 | target/riscv: Add the mcountinhibit CSR | Alistair Francis | 1 | -2/+15 |
2019-06-10 | target/riscv: Use env_cpu, env_archcpu | Richard Henderson | 1 | -6/+6 |
2019-05-24 | target/riscv: Only flush TLB if SATP.ASID changes | Jonathan Behrens | 1 | -1/+3 |
2019-05-24 | target/riscv: More accurate handling of `sip` CSR | Jonathan Behrens | 1 | -2/+5 |
2019-05-24 | target/riscv: Allow setting mstatus virtulisation bits | Alistair Francis | 1 | -9/+8 |
2019-05-24 | target/riscv: Trigger interrupt on MIP update asynchronously | Alistair Francis | 1 | -2/+0 |
2019-03-19 | RISC-V: Add support for vectored interrupts | Michael Clark | 1 | -6/+6 |
2019-03-19 | RISC-V: Allow interrupt controllers to claim interrupts | Michael Clark | 1 | -8/+2 |
2019-03-19 | RISC-V: Add debug support for accessing CSRs. | Jim Wilson | 1 | -7/+25 |
2019-02-11 | target/riscv: fix counter-enable checks in ctr() | Xi Wang | 1 | -3/+9 |
2019-02-11 | RISC-V: Add misa runtime write support | Michael Clark | 1 | -1/+53 |
2019-02-11 | RISC-V: Use riscv prefix consistently on cpu helpers | Michael Clark | 1 | -4/+4 |
2019-02-11 | RISC-V: Implement mstatus.TSR/TW/TVM | Michael Clark | 1 | -4/+13 |
2019-02-11 | RISC-V: Mark mstatus.fs dirty | Richard Henderson | 1 | -12/+0 |
2019-01-09 | RISC-V: Implement existential predicates for CSRs | Michael Clark | 1 | -76/+93 |
2019-01-09 | RISC-V: Implement atomic mip/sip CSR updates | Michael Clark | 1 | -28/+28 |
2019-01-08 | RISC-V: Implement modular CSR helper interface | Michael Clark | 1 | -0/+846 |