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path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé1-0/+1
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel1-0/+203
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel1-0/+177
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel1-0/+156
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel1-0/+23
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel1-1/+127
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-103/+457
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-13/+30
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel1-7/+11
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel1-1/+1
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei1-6/+22
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-1/+12
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+19
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei1-0/+3
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-0/+2
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei1-0/+19
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-1/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-1/+5
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot1-30/+165
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+17
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-1/+5
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang1-0/+5
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu1-0/+7
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei1-0/+17
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang1-13/+0
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei1-1/+1
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-1/+11
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo1-0/+285
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-15/+22
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+3
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-12/+12
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-15/+29
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng1-12/+12
2021-09-21target/riscv: Fix satp writeLIU Zhiwei1-1/+1
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson1-18/+8
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson1-8/+15
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei1-3/+5
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng1-1/+1
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins1-23/+31
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng1-24/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-4/+15
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-2/+10
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis1-1/+8
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying1-0/+24
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-19/+18
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis1-255/+374
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis1-1/+5
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