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path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
2020-07-02target/riscv: support vector extension csrLIU Zhiwei1-1/+74
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-113/+25
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-4/+82
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+25
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis1-4/+20
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis1-0/+3
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis1-0/+27
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis1-0/+116
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis1-2/+134
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis1-4/+14
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis1-2/+5
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung1-2/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-1/+1
2019-10-28riscv: Skip checking CSR privilege level in debugger modeBin Meng1-1/+4
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis1-1/+1
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis1-9/+11
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt1-0/+6
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis1-5/+12
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis1-2/+15
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson1-6/+6
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens1-1/+3
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens1-2/+5
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis1-9/+8
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis1-2/+0
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark1-6/+6
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark1-8/+2
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson1-7/+25
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang1-3/+9
2019-02-11RISC-V: Add misa runtime write supportMichael Clark1-1/+53
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark1-4/+4
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark1-4/+13
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson1-12/+0
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark1-76/+93
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark1-28/+28
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark1-0/+846
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