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path: root/target/riscv/csr.c
AgeCommit message (Expand)AuthorFilesLines
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo1-0/+285
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-15/+22
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+3
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-12/+12
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-15/+29
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng1-12/+12
2021-09-21target/riscv: Fix satp writeLIU Zhiwei1-1/+1
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson1-18/+8
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson1-8/+15
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei1-3/+5
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng1-1/+1
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins1-23/+31
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng1-24/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-4/+15
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-2/+10
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis1-1/+8
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying1-0/+24
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-19/+18
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis1-255/+374
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis1-1/+5
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis1-36/+44
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-32/+10
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer1-34/+34
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer1-3/+4
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang1-1/+1
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng1-84/+248
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng1-9/+1
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis1-85/+91
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang1-1/+1
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-8/+10
2020-10-05icount: rename functions to be consistent with the module nameClaudio Fontana1-2/+2
2020-10-05cpu-timers, icount: new modulesClaudio Fontana1-2/+2
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-2/+2
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-1/+63
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis1-23/+23
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis1-0/+40
2020-08-25target/riscv: Only support little endian guestsAlistair Francis1-0/+5
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis1-0/+9
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis1-3/+3
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis1-1/+0
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li1-1/+1
2020-07-02target/riscv: support vector extension csrLIU Zhiwei1-1/+74
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-113/+25
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-4/+82
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+25
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis1-4/+20
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis1-0/+3
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis1-0/+27
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis1-0/+116
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