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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis1-1/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-53/+29
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel1-6/+1
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis1-3/+5
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis1-1/+2
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal1-1/+8
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-0/+5
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-2/+2
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+17
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis1-19/+174
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis1-0/+61
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis1-0/+18
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis1-0/+18
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis1-2/+5
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-30/+18
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio1-1/+4
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt1-4/+7
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt1-3/+9
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng1-5/+5
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis1-0/+10
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing1-0/+10
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary1-2/+1
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary1-1/+9
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary1-1/+9
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary1-3/+6
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary1-0/+1
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark1-0/+16
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson1-6/+4
2019-05-24target/riscv: Improve the scause logicAlistair Francis1-1/+1
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis1-6/+27
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-6/+0
2019-05-10target/riscv: Convert to CPUClass::tlb_fillRichard Henderson1-25/+21
2019-03-19RISC-V: Update load reservation comment in do_interruptMichael Clark1-1/+7
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark1-9/+3
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark1-91/+54
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark1-2/+2
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark1-0/+11
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark1-5/+5
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark1-1/+2
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark1-2/+2
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark1-8/+10
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