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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+10
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis1-5/+7
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang1-1/+2
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-36/+24
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis1-1/+1
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-28/+7
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang1-9/+27
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer1-1/+3
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer1-1/+1
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis1-1/+7
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+3
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-2/+2
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-10/+6
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis1-2/+3
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis1-4/+20
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis1-35/+25
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis1-0/+18
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li1-2/+8
2020-08-21target/riscv: Fix the translation of physical addressZong Li1-2/+3
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis1-1/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-53/+29
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel1-6/+1
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis1-3/+5
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis1-1/+2
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal1-1/+8
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel1-0/+5
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-2/+2
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+17
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis1-19/+174
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis1-0/+61
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis1-0/+18
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis1-0/+18
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis1-2/+5
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis1-30/+18
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio1-1/+4
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt1-4/+7
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt1-3/+9
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng1-5/+5
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis1-0/+10
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