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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson1-20/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-25/+1
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins1-20/+8
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-0/+18
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-2/+1
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+33
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-6/+6
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson1-0/+46
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-5/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-8/+24
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis1-9/+15
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink1-8/+12
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis1-2/+2
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-6/+6
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer1-13/+8
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer1-1/+1
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer1-11/+14
2021-03-22target/riscv: add log of PMP permission checkingJim Shu1-0/+12
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu1-21/+63
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+10
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis1-5/+7
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang1-1/+2
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-36/+24
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis1-1/+1
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-28/+7
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang1-9/+27
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer1-1/+3
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer1-1/+1
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis1-1/+7
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+3
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-2/+2
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-10/+6
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis1-2/+3
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis1-4/+20
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis1-35/+25
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis1-0/+18
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li1-2/+8
2020-08-21target/riscv: Fix the translation of physical addressZong Li1-2/+3
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis1-2/+7
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis1-1/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-53/+29
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel1-6/+1
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis1-3/+5
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis1-1/+2
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal1-1/+8
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