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path: root/target/riscv/cpu_helper.c
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2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt1-2/+14
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li1-0/+6
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li1-2/+8
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt1-1/+1
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li1-1/+1
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza1-1/+1
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza1-1/+1
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza1-1/+1
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza1-1/+1
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich1-0/+6
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel1-2/+0
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-5/+5
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell1-8/+18
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu1-1/+1
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei1-2/+1
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei1-0/+3
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-0/+6
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei1-7/+9
2023-01-04target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mipRichard Henderson1-9/+1
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-6/+3
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra1-0/+25
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-3/+8
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-1/+2
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel1-6/+246
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel1-69/+65
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson1-1/+1
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker1-1/+1
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-0/+1
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel1-2/+1
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang1-2/+2
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson1-3/+3
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-1/+5
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-1/+3
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-3/+15
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li1-0/+3
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-1/+12
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-5/+5
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-21/+260
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel1-0/+14
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel1-0/+13
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-3/+34
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-2/+1
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-18/+6
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+43
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-32/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-1/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-1/+4
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