riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-07-02	target/riscv: support vector extension csr	LIU Zhiwei	1	-0/+15
2020-02-27	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	Alistair Francis	1	-0/+11
2020-02-27	target/riscv: Add support for the 32-bit MSTATUSH CSR	Alistair Francis	1	-0/+3
2020-02-27	target/riscv: Add virtual register swapping function	Alistair Francis	1	-0/+7
2020-02-27	target/riscv: Add the force HS exception mode	Alistair Francis	1	-0/+6
2020-02-27	target/riscv: Add the virtulisation mode	Alistair Francis	1	-0/+3
2020-02-27	target/riscv: Rename the H irqs to VS irqs	Alistair Francis	1	-6/+6
2020-02-27	target/riscv: Add support for the new execption numbers	Alistair Francis	1	-16/+19
2020-02-27	target/riscv: Add the Hypervisor CSRs to CPUState	Alistair Francis	1	-13/+21
2019-09-17	target/riscv: Update the Hypervisor CSRs to v0.4	Alistair Francis	1	-17/+18
2019-06-25	target/riscv: Add the mcountinhibit CSR	Alistair Francis	1	-0/+1
2019-06-12	Supply missing header guards	Markus Armbruster	1	-0/+5
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis	1	-0/+11
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis	1	-0/+18
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis	1	-3/+6
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis	1	-3/+2
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis	1	-1/+1
2019-03-19	RISC-V: Fixes to CSR_* register macros.	Jim Wilson	1	-2/+33
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark	1	-0/+11
2018-10-17	RISC-V: Update CSR and interrupt definitions	Michael Clark	1	-318/+365
2018-09-04	RISC-V: Improve page table walker spec compliance	Michael Clark	1	-2/+0
2018-03-07	RISC-V CPU Core Definition	Michael Clark	1	-0/+411