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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng1-1/+3
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang1-4/+4
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng1-0/+5
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis1-0/+8
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra1-0/+5
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra1-0/+2
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra1-0/+1
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra1-2/+5
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-5/+5
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-1/+1
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé1-3/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-3/+2
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-0/+15
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel1-0/+1
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel1-0/+7
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel1-0/+2
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-7/+7
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-0/+12
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel1-0/+23
2022-02-16target/riscv: Add AIA cpu featureAnup Patel1-1/+2
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel1-0/+5
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-0/+5
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+3
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich1-37/+41
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei1-1/+0
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei1-0/+5
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-0/+1
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-1/+2
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+4
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-0/+31
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-0/+1
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang1-0/+7
2022-01-21target/riscv: Add host cpu typeYifei Jiang1-0/+1
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-0/+3
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+2
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot1-0/+7
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+5
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot1-0/+4
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-0/+3
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot1-0/+1
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-0/+2
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang1-0/+1
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang1-9/+18
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang1-12/+14
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