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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-1/+1
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-1/+1
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang1-0/+3
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng1-0/+1
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+1
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng1-2/+0
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis1-6/+0
2021-05-11target/riscv: Add a config option for ePMPHou Weiying1-0/+1
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying1-0/+1
2021-05-11target/riscv: Add the ePMP featureAlistair Francis1-0/+1
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-4/+7
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis1-6/+8
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis1-1/+2
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K1-0/+1
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-3/+1
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer1-0/+4
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang1-0/+4
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng1-0/+2
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng1-0/+1
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng1-0/+8
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis1-0/+2
2020-12-17target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis1-0/+6
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-0/+12
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-2/+1
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis1-1/+3
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-13/+11
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang1-3/+7
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost1-1/+1
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell1-2/+6
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-2/+4
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang1-0/+1
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost1-4/+2
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-6/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-4/+7
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis1-0/+2
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang1-1/+1
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei1-1/+3
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei1-9/+54
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei1-0/+5
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei1-0/+12
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis1-0/+1
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-1/+0
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis1-7/+0
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton1-0/+1
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell1-1/+1
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell1-1/+1
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