riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-27	target/riscv: Add the force HS exception mode	Alistair Francis	1	-0/+2
2020-02-27	target/riscv: Add the virtulisation mode	Alistair Francis	1	-0/+4
2020-02-27	target/riscv: Add the Hypervisor CSRs to CPUState	Alistair Francis	1	-0/+21
2020-02-27	target/riscv: Add the Hypervisor extension	Alistair Francis	1	-0/+1
2020-02-27	target/riscv: Convert MIP CSR to target_ulong	Alistair Francis	1	-1/+1
2020-01-16	target/riscv: Fix tb->flags FS status	ShihPo Hung	1	-4/+1
2019-11-14	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis	1	-9/+0
2019-10-28	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt	1	-2/+5
2019-09-17	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point	Alistair Francis	1	-1/+1
2019-09-17	target/riscv: Create function to test if FP is enabled	Alistair Francis	1	-1/+5
2019-08-21	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster	1	-1/+1
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée	1	-1/+1
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt	1	-0/+1
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt	1	-0/+1
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis	1	-0/+1
2019-06-25	target/riscv: Remove user version information	Alistair Francis	1	-2/+0
2019-06-24	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis	1	-0/+1
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis	1	-6/+7
2019-06-23	RISC-V: Check PMP during Page Table Walks	Hesham Almatary	1	-0/+1
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark	1	-0/+2
2019-06-23	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis	1	-0/+11
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson	1	-3/+0
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson	1	-0/+1
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson	1	-2/+0
2019-06-10	target/riscv: Use env_cpu, env_archcpu	Richard Henderson	1	-5/+0
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	1	-1/+0
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-2/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	1	-17/+4
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	1	-0/+2
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis	1	-0/+8
2019-05-10	target/riscv: Convert to CPUClass::tlb_fill	Richard Henderson	1	-2/+3
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-1/+1
2019-03-19	RISC-V: linux-user support for RVE ABI	Kito Cheng	1	-0/+4
2019-03-19	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark	1	-0/+2
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	1	-0/+2
2019-03-19	RISC-V: Add debug support for accessing CSRs.	Jim Wilson	1	-0/+5
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark	1	-1/+3
2019-02-11	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark	1	-11/+10
2019-02-11	RISC-V: Split out mstatus_fs from tb_flags	Richard Henderson	1	-3/+3
2019-01-09	RISC-V: Implement existential predicates for CSRs	Michael Clark	1	-2/+4
2019-01-08	RISC-V: Implement modular CSR helper interface	Michael Clark	1	-3/+32
2018-10-17	RISC-V: Allow setting and clearing multiple irqs	Michael Clark	1	-9/+13
2018-09-05	riscv: remove define cpu_init()	Igor Mammedov	1	-1/+0
2018-09-04	RISC-V: Update address bits to support sv39 and sv48	Michael Clark	1	-4/+4
2018-05-06	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	Michael Clark	1	-4/+2
2018-05-06	RISC-V: Update E and I extension order	Michael Clark	1	-0/+1
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark	1	-1/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1