| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-09-07 | target/riscv: rvv: Add mask agnostic for vv instructions | Yueh-Ting (eop) Chen | 1 | -0/+2 |
| 2022-09-07 | target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() | Anup Patel | 1 | -0/+5 |
| 2022-07-03 | target/riscv: Support mcycle/minstret write operation | Atish Patra | 1 | -7/+16 |
| 2022-07-03 | target/riscv: Add support for hpmcounters/hpmevents | Atish Patra | 1 | -0/+11 |
| 2022-07-03 | target/riscv: Implement mcountinhibit CSR | Atish Patra | 1 | -0/+2 |
| 2022-07-03 | target/riscv: pmu: Make number of counters configurable | Atish Patra | 1 | -1/+1 |
| 2022-07-03 | target/riscv: pmu: Rename the counters extension to pmu | Atish Patra | 1 | -1/+1 |
| 2022-06-10 | target/riscv: rvv: Add tail agnostic for vv instructions | eopXD | 1 | -0/+2 |
| 2022-06-10 | target/riscv: Wake on VS-level external interrupts | Andrew Bresticker | 1 | -0/+1 |
| 2022-06-10 | target/riscv: add support for zmmul extension v0.1 | Weiwei Li | 1 | -0/+1 |
| 2022-05-24 | target/riscv: Set [m|s]tval for both illegal and virtual instruction traps | Anup Patel | 1 | -1/+7 |
| 2022-05-24 | target/riscv: Fix typo of mimpid cpu option | Frank Chang | 1 | -1/+1 |
| 2022-05-24 | target/riscv: Add short-isa-string option | Tsukasa OI | 1 | -0/+2 |
| 2022-04-29 | target/riscv: rvk: add cfg properties for zbk* and zk* | Weiwei Li | 1 | -0/+13 |
| 2022-04-29 | target/riscv: Support configuarable marchid, mvendorid, mipid CSR values | Frank Chang | 1 | -0/+4 |
| 2022-04-22 | target/riscv: cpu: Add a config option for native debug | Bin Meng | 1 | -1/+3 |
| 2022-04-22 | hw/intc: Make RISC-V ACLINT mtime MMIO register writable | Frank Chang | 1 | -4/+4 |
| 2022-04-22 | target/riscv: Add initial support for the Sdtrig extension | Bin Meng | 1 | -0/+5 |
| 2022-04-22 | target/riscv: Allow software access to MIP SEIP | Alistair Francis | 1 | -0/+8 |
| 2022-04-22 | target/riscv: Add *envcfg* CSRs support | Atish Patra | 1 | -0/+5 |
| 2022-04-22 | target/riscv: Introduce privilege version field in the CSR ops. | Atish Patra | 1 | -0/+2 |
| 2022-04-22 | target/riscv: Add the privileged spec version 1.12.0 | Atish Patra | 1 | -0/+1 |
| 2022-04-22 | target/riscv: Define simpler privileged spec version numbering | Atish Patra | 1 | -2/+5 |
| 2022-04-21 | compiler.h: replace QEMU_NORETURN with G_NORETURN | Marc-André Lureau | 1 | -5/+5 |
| 2022-04-06 | Move CPU softfloat unions to cpu-float.h | Marc-André Lureau | 1 | -1/+1 |
| 2022-03-06 | target: Use ArchCPU as interface to target CPU | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2022-03-06 | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro | Philippe Mathieu-Daudé | 1 | -3/+1 |
| 2022-03-06 | target: Use CPUArchState as interface to target-specific CPU state | Philippe Mathieu-Daudé | 1 | -3/+2 |
| 2022-03-03 | target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} | Weiwei Li | 1 | -0/+4 |
| 2022-02-16 | target/riscv: add support for svinval extension | Weiwei Li | 1 | -0/+1 |
| 2022-02-16 | target/riscv: Ignore reserved bits in PTE for RV64 | Guo Ren | 1 | -0/+15 |
| 2022-02-16 | target/riscv: Allow users to force enable AIA CSRs in HART | Anup Patel | 1 | -0/+1 |
| 2022-02-16 | target/riscv: Implement AIA xiselect and xireg CSRs | Anup Patel | 1 | -0/+7 |
| 2022-02-16 | target/riscv: Implement AIA hvictl and hviprioX CSRs | Anup Patel | 1 | -0/+2 |
| 2022-02-16 | target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 | Anup Patel | 1 | -7/+7 |
| 2022-02-16 | target/riscv: Implement AIA local interrupt priorities | Anup Patel | 1 | -0/+12 |
| 2022-02-16 | target/riscv: Allow AIA device emulation to set ireg rmw callback | Anup Patel | 1 | -0/+23 |
| 2022-02-16 | target/riscv: Add AIA cpu feature | Anup Patel | 1 | -1/+2 |
| 2022-02-16 | target/riscv: Allow setting CPU feature from machine/device emulation | Anup Patel | 1 | -0/+5 |
| 2022-02-16 | target/riscv: Implement hgeie and hgeip CSRs | Anup Patel | 1 | -0/+5 |
| 2022-02-16 | target/riscv: Add XVentanaCondOps custom extension | Philipp Tomsich | 1 | -0/+3 |
| 2022-02-16 | target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC... | Philipp Tomsich | 1 | -37/+41 |
| 2022-01-21 | target/riscv: Remove VILL field in VTYPE | LIU Zhiwei | 1 | -1/+0 |
| 2022-01-21 | target/riscv: Adjust vsetvl according to XLEN | LIU Zhiwei | 1 | -0/+5 |
| 2022-01-21 | target/riscv: Split out the vill from vtype | LIU Zhiwei | 1 | -0/+1 |
| 2022-01-21 | target/riscv: Split pm_enabled into mask and base | LIU Zhiwei | 1 | -1/+2 |
| 2022-01-21 | target/riscv: Create current pm fields in env | LIU Zhiwei | 1 | -0/+4 |
| 2022-01-21 | target/riscv: Create xl field in env | LIU Zhiwei | 1 | -0/+31 |
| 2022-01-21 | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V | Frank Chang | 1 | -0/+1 |
| 2022-01-21 | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V | Frank Chang | 1 | -0/+1 |
