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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+1
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei1-0/+1
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei1-0/+2
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-0/+2
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale1-0/+4
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell1-2/+2
2022-10-06dump: Replace opaque DumpState pointer with a typed oneJanosch Frank1-2/+2
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang1-1/+5
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang1-1/+1
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis1-2/+1
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+25
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-0/+4
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+5
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra1-2/+0
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-2/+2
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel1-0/+5
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra1-7/+16
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra1-0/+11
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra1-0/+2
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra1-1/+1
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra1-1/+1
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker1-0/+1
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li1-0/+1
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-1/+7
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang1-1/+1
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI1-0/+2
2022-04-29target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li1-0/+13
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang1-0/+4
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng1-1/+3
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang1-4/+4
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng1-0/+5
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis1-0/+8
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra1-0/+5
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra1-0/+2
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra1-0/+1
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra1-2/+5
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-5/+5
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-1/+1
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé1-3/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-3/+2
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-0/+15
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel1-0/+1
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel1-0/+7
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel1-0/+2
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