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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak1-0/+38
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza1-4/+16
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei1-1/+1
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li1-2/+3
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza1-31/+10
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza1-9/+8
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza1-2/+1
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza1-52/+0
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza1-7/+5
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza1-3/+3
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza1-5/+4
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza1-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza1-8/+7
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza1-13/+13
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza1-9/+8
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza1-5/+4
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza1-8/+8
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza1-0/+65
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza1-67/+65
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza1-2/+17
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza1-38/+56
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-1/+2
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-1/+1
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-20/+20
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-1/+1
2023-05-05target/riscv: Add support for ZceWeiwei Li1-0/+12
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li1-0/+14
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li1-0/+43
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li1-3/+3
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei1-4/+4
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti1-24/+69
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti1-0/+214
2023-03-06riscv: Pass Object to register_cpu_props instead of DeviceStateAlexandre Ghiti1-14/+15
2023-03-05target/riscv: cpu: Implement get_arch_id callbackMayuresh Chitale1-0/+8
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+3
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+4
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-43/+91
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt1-0/+8
2023-03-01target/riscv: Export Svadu propertyWeiwei Li1-0/+3
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li1-2/+4
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li1-0/+3
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+2
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt1-28/+71
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li1-0/+7
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li1-22/+22
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li1-0/+14
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li1-3/+18
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