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2017-02-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170222' into...Peter Maydell13-35/+615
2017-02-22hw/ppc/spapr: Check for valid page size when hot plugging memoryThomas Huth2-4/+35
2017-02-22target-ppc: fix Book-E TLB matchingAlex Zuepke1-1/+1
2017-02-22target/ppc/POWER9: Direct all instr and data storage interrupts to the hypvSuraj Jitindar Singh1-2/+18
2017-02-22target/ppc/POWER9: Adapt LPCR handling for POWER9Suraj Jitindar Singh3-6/+44
2017-02-22target/ppc/POWER9: Add ISAv3.00 MMU definitionSuraj Jitindar Singh3-3/+7
2017-02-22target/ppc: Fix LPCR DPFD mask defineSuraj Jitindar Singh1-1/+1
2017-02-22target-ppc: Add xscvqpudz and xscvqpuwz instructionsBharata B Rao4-0/+8
2017-02-22target-ppc: Implement round to odd variants of quad FP instructionsBharata B Rao2-23/+21
2017-02-22target-ppc: add wait instructionNikunj A Dadhania1-0/+1
2017-02-22target-ppc: add slbsync implementationNikunj A Dadhania1-0/+12
2017-02-22target-ppc: add slbieg instructionNikunj A Dadhania3-2/+29
2017-02-22target-ppc: generate exception for copy/pasteNikunj A Dadhania1-0/+15
2017-02-22target-ppc: implement store atomic instructionBalamuruhan S1-0/+52
2017-02-22target-ppc: implement load atomic instructionBalamuruhan S2-0/+61
2017-02-22target-ppc: Add xsmaxjdp and xsminjdp instructionsBharata B Rao4-0/+61
2017-02-22target-ppc: Add xsmaxcdp and xsmincdp instructionsBharata B Rao4-0/+44
2017-02-22ppc: implement xssubqp instructionJose Ricardo Ziviani4-0/+37
2017-02-22ppc: implement xssqrtqp instructionJose Ricardo Ziviani4-0/+41
2017-02-22ppc: implement xsrqpxp instructionJose Ricardo Ziviani4-0/+59
2017-02-22ppc: implement xsrqpi[x] instructionJose Ricardo Ziviani5-0/+75
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth1-0/+4
2017-02-02ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth1-13/+23
2017-02-02target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh1-1/+1
2017-02-02target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh1-2/+2
2017-02-02tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh1-0/+5
2017-02-02target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh1-0/+3
2017-02-02target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania5-8/+69
2017-02-02target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania5-2/+55
2017-01-31target/ppc/cpu-models: Fix/remove bad CPU aliasesThomas Huth1-20/+2
2017-01-31target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth1-22/+0
2017-01-31spapr: clock should count only if vm is runningLaurent Vivier1-0/+3
2017-01-31target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh2-0/+3
2017-01-31powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh1-1/+1
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania4-9/+24
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao4-0/+38
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao4-0/+39
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao4-0/+31
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao1-12/+8
2017-01-31ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani4-1/+57
2017-01-31ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani4-2/+45
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao4-0/+46
2017-01-31target-ppc: Add xvxsigdp instructionNikunj A Dadhania2-0/+41
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania4-0/+24
2017-01-31target-ppc: Add xvxexpdp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xvxexpsp instructionNikunj A Dadhania2-0/+18
2017-01-31target-ppc: Add xviexpdp instructionNikunj A Dadhania2-0/+27
2017-01-31target-ppc: Add xviexpsp instructionNikunj A Dadhania2-0/+28
2017-01-31target-ppc: Add xsiexpqp instructionNikunj A Dadhania2-0/+23
2017-01-31target-ppc: Add xsiexpdp instructionNikunj A Dadhania2-0/+21
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