| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-03-12 | target/ppc: Optimize x[sv]xsigdp using deposit_i64() | Philippe Mathieu-Daudé | 1 | -8/+4 |
| 2019-03-12 | target/ppc: Optimize xviexpdp() using deposit_i64() | Philippe Mathieu-Daudé | 1 | -11/+3 |
| 2019-03-12 | target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_c... | Mark Cave-Ayland | 1 | -30/+4 |
| 2019-03-12 | target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr... | Mark Cave-Ayland | 1 | -5/+0 |
| 2019-03-12 | target/ppc: introduce avr_full_offset() function | Mark Cave-Ayland | 2 | -16/+11 |
| 2019-03-12 | target/ppc: introduce single vsrl_offset() function | Mark Cave-Ayland | 1 | -6/+6 |
| 2019-02-18 | target/ppc: convert vmin* and vmax* to vector operations | Richard Henderson | 1 | -16/+16 |
| 2019-02-18 | target/ppc: convert vadd*s and vsub*s to vector operations | Richard Henderson | 1 | -12/+45 |
| 2019-02-18 | target/ppc: Add helper_mfvscr | Richard Henderson | 1 | -1/+1 |
| 2019-02-18 | target/ppc: Pass integer to helper_mtvscr | Richard Henderson | 1 | -4/+13 |
| 2019-02-18 | target/ppc: convert xxsel to vector operations | Richard Henderson | 1 | -28/+27 |
| 2019-02-18 | target/ppc: convert xxspltw to vector operations | Richard Henderson | 1 | -25/+11 |
| 2019-02-18 | target/ppc: convert xxspltib to vector operations | Richard Henderson | 1 | -8/+5 |
| 2019-02-18 | target/ppc: convert VSX logical operations to vector operations | Richard Henderson | 1 | -26/+17 |
| 2019-02-18 | target/ppc: convert vsplt[bhw] to use vector operations | Richard Henderson | 1 | -19/+27 |
| 2019-02-18 | target/ppc: convert vspltis[bhw] to use vector operations | Richard Henderson | 1 | -28/+8 |
| 2019-02-18 | target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper... | Mark Cave-Ayland | 1 | -8/+8 |
| 2019-02-18 | target/ppc: convert VMX logical instructions to use vector operations | Mark Cave-Ayland | 1 | -31/+16 |
| 2019-01-09 | target/ppc: move FP and VMX registers into aligned vsr register array | Mark Cave-Ayland | 3 | -4/+9 |
| 2019-01-09 | target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env | Mark Cave-Ayland | 1 | -2/+2 |
| 2019-01-09 | target/ppc: introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for V... | Mark Cave-Ayland | 1 | -224/+638 |
| 2019-01-09 | target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register ac... | Mark Cave-Ayland | 1 | -33/+114 |
| 2019-01-09 | target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access | Mark Cave-Ayland | 1 | -110/+376 |
| 2018-12-21 | Changes requirement for "vsubsbs" instruction | Paul A. Clarke | 1 | -1/+1 |
| 2018-11-08 | target/ppc: add external PID support | Roman Kapl | 2 | -0/+36 |
| 2018-08-21 | target/ppc: Use non-arithmetic conversions for fp load/store | Richard Henderson | 1 | -16/+10 |
| 2018-02-16 | target/ppc: convert to DisasContextBase | Emilio G. Cota | 1 | -8/+8 |
| 2017-07-19 | target/ppc: optimize various functions using extract op | Philippe Mathieu-Daudé | 1 | -16/+8 |
| 2017-02-22 | target-ppc: Add xscvqpudz and xscvqpuwz instructions | Bharata B Rao | 2 | -0/+4 |
| 2017-02-22 | target-ppc: Implement round to odd variants of quad FP instructions | Bharata B Rao | 1 | -1/+1 |
| 2017-02-22 | target-ppc: Add xsmaxjdp and xsminjdp instructions | Bharata B Rao | 2 | -0/+4 |
| 2017-02-22 | target-ppc: Add xsmaxcdp and xsmincdp instructions | Bharata B Rao | 2 | -0/+4 |
| 2017-02-22 | ppc: implement xssubqp instruction | Jose Ricardo Ziviani | 2 | -0/+2 |
| 2017-02-22 | ppc: implement xssqrtqp instruction | Jose Ricardo Ziviani | 2 | -0/+2 |
| 2017-02-22 | ppc: implement xsrqpxp instruction | Jose Ricardo Ziviani | 2 | -0/+2 |
| 2017-02-22 | ppc: implement xsrqpi[x] instruction | Jose Ricardo Ziviani | 2 | -0/+14 |
| 2017-02-02 | target-ppc: Add xststdc[sp, dp, qp] instructions | Nikunj A Dadhania | 2 | -0/+7 |
| 2017-02-02 | target-ppc: Add xvtstdc[sp,dp] instructions | Nikunj A Dadhania | 2 | -0/+10 |
| 2017-01-31 | target-ppc: Add xvcv[hpsp, sphp] instructions | Nikunj A Dadhania | 2 | -0/+4 |
| 2017-01-31 | target-ppc: Add xsmulqp instruction | Bharata B Rao | 2 | -0/+2 |
| 2017-01-31 | target-ppc: Add xsdivqp instruction | Bharata B Rao | 2 | -0/+2 |
| 2017-01-31 | target-ppc: Add xscvsdqp and xscvudqp instructions | Bharata B Rao | 2 | -0/+4 |
| 2017-01-31 | ppc: Implement bcdutrunc. instruction | Jose Ricardo Ziviani | 2 | -1/+5 |
| 2017-01-31 | ppc: Implement bcdtrunc. instruction | Jose Ricardo Ziviani | 2 | -2/+7 |
| 2017-01-31 | target-ppc: Add xscvqps[d,w]z instructions | Bharata B Rao | 2 | -0/+4 |
| 2017-01-31 | target-ppc: Add xvxsigdp instruction | Nikunj A Dadhania | 2 | -0/+41 |
| 2017-01-31 | target-ppc: Add xvxsigsp instruction | Nikunj A Dadhania | 2 | -0/+3 |
| 2017-01-31 | target-ppc: Add xvxexpdp instruction | Nikunj A Dadhania | 2 | -0/+18 |
| 2017-01-31 | target-ppc: Add xvxexpsp instruction | Nikunj A Dadhania | 2 | -0/+18 |
| 2017-01-31 | target-ppc: Add xviexpdp instruction | Nikunj A Dadhania | 2 | -0/+27 |
