| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-01-31 | ppc: Implement bcdutrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+4 |
| 2017-01-31 | ppc: Implement bcdtrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+5 |
| 2017-01-31 | ppc: Implement bcdsr. instruction | Jose Ricardo Ziviani | 1 | -0/+1 |
| 2017-01-31 | ppc: Implement bcdus. instruction | Jose Ricardo Ziviani | 1 | -0/+3 |
| 2017-01-31 | ppc: Implement bcds. instruction | Jose Ricardo Ziviani | 1 | -0/+3 |
| 2017-01-31 | target-ppc: add vextu[bhw][lr]x instructions | Avinesh Kumar | 1 | -0/+23 |
| 2017-01-31 | target-ppc: Implement bcdsetsgn. instruction | Jose Ricardo Ziviani | 1 | -0/+8 |
| 2017-01-31 | target-ppc: Implement bcdcpsgn. instruction | Jose Ricardo Ziviani | 1 | -0/+3 |
| 2017-01-31 | target-ppc: Implement bcdctsq. instruction | Jose Ricardo Ziviani | 1 | -0/+7 |
| 2017-01-31 | target-ppc: Implement bcdcfsq. instruction | Jose Ricardo Ziviani | 1 | -0/+7 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+1113 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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