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path: root/target/ppc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2018-02-16target/ppc: convert to TranslatorOpsEmilio G. Cota1-162/+167
2018-02-16target/ppc: convert to DisasContextBaseEmilio G. Cota1-62/+67
2018-01-20target/ppc: add support for hypervisor doorbells on book3s CPUsCédric Le Goater1-2/+23
2018-01-20target-ppc: optimize cmp translationpbonzini@redhat.com1-17/+12
2018-01-20target/ppc: msgsnd and msgclr instructions need hypervisor privilegeCédric Le Goater1-2/+2
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-1/+1
2017-12-15target/ppc: Use tcg_gen_lookup_and_goto_ptrRichard Henderson1-15/+8
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-4/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-25target/ppc: Convert to disas_set_info hookRichard Henderson1-4/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+0
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson1-2/+2
2017-10-17target/ppc: Fix carry flag setting for shift algebraic instructionsSandipan Das1-0/+12
2017-08-31ppc: use DIV_ROUND_UPMarc-André Lureau1-1/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-19target/ppc: optimize various functions using extract opPhilippe Mathieu-Daudé1-14/+7
2017-05-11target/ppc: Change tlbie invalid fields for POWER9 supportSuraj Jitindar Singh1-0/+2
2017-05-11target/ppc: Update tlbie to check privilege level based on GTSESuraj Jitindar Singh1-1/+8
2017-05-11target/ppc: Generate fence operationsNikunj A Dadhania1-0/+8
2017-05-11target/ppc: Emulate LL/SC using cmpxchg helpersNikunj A Dadhania1-6/+23
2017-03-14target/ppc: fix cpu_ov setting for 32-bitNikunj A Dadhania1-1/+1
2017-03-03spapr: Small cleanup of PPC MMU enumsSam Bobroff1-8/+6
2017-03-03target/ppc: Don't gen an SDR1 on POWER9 and rework register creationSuraj Jitindar Singh1-2/+5
2017-03-01target/ppc: add mcrxrx instructionNikunj A Dadhania1-0/+23
2017-03-01target/ppc: add ov32 flag in divide operationsNikunj A Dadhania1-2/+8
2017-03-01target/ppc: add ov32 flag for multiply low insnsNikunj A Dadhania1-0/+6
2017-03-01target/ppc: use tcg ops for neg instructionNikunj A Dadhania1-1/+4
2017-03-01target/ppc: update overflow flags for add/subNikunj A Dadhania1-2/+9
2017-03-01target/ppc: update ca32 in arithmetic substractNikunj A Dadhania1-1/+10
2017-03-01target/ppc: update ca32 in arithmetic addNikunj A Dadhania1-0/+21
2017-03-01target/ppc: support for 32-bit carry and overflowNikunj A Dadhania1-3/+18
2017-03-01target/ppc: optimize gen_write_xer()Nikunj A Dadhania1-6/+3
2017-02-22target-ppc: add wait instructionNikunj A Dadhania1-0/+1
2017-02-22target-ppc: add slbsync implementationNikunj A Dadhania1-0/+12
2017-02-22target-ppc: add slbieg instructionNikunj A Dadhania1-0/+14
2017-02-22target-ppc: generate exception for copy/pasteNikunj A Dadhania1-0/+15
2017-02-22target-ppc: implement store atomic instructionBalamuruhan S1-0/+52
2017-02-22target-ppc: implement load atomic instructionBalamuruhan S1-0/+59
2017-02-02tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh1-0/+5
2017-02-02target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh1-0/+3
2017-01-31target-ppc: implement stop instructionNikunj A Dadhania1-0/+6
2017-01-31target-ppc: implement lxv/lxvx and stxv/stxvxNikunj A Dadhania1-2/+8
2017-01-31target-ppc: implement stxsd and stxsspNikunj A Dadhania1-0/+34
2017-01-31target-ppc: implement lxsd and lxssp instructionsNikunj A Dadhania1-0/+25
2017-01-31target-ppc: rename CRF_* defines as CRF_*_BITNikunj A Dadhania1-7/+7
2017-01-31target-ppc: Consolidate instruction decode helpersBharata B Rao1-151/+0
2017-01-10target-ppc: Use ctpop helperRichard Henderson1-1/+5
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