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2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé1-1/+0
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-8-philmd@linaro.org>
2023-06-10target/ppc: Move ppcemb_tlb_search() to mmu_common.cBALATON Zoltan1-21/+0
This function is the only reason why ppcemb_tlb_check() is not static to mmu_common.c but it also better fits in mmu_common.c so move it there. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <b64fd712a773558dea9b84945c57785546c0ae2e.1685448535.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-06-10target/ppc: Remove "ext" parameter of ppcemb_tlb_check()BALATON Zoltan1-1/+1
This is only used by one caller so simplify function by removing this parameter and move the operation to the single place where it's used. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <b21f11ae20e8a8c2e8b5d943f2bff12b5356005a.1685448535.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-06-10target/ppc: Remove single use functionBALATON Zoltan1-10/+1
The get_physical_address() function is a trivial wrapper of get_physical_address_wtlb() that is only used once. Remove it and call get_physical_address_wtlb() directly instead. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <302697d63d26caebefaeee1e45352145ebd0318a.1685448535.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-2/+2
The 'hwaddr' type is defined in "exec/hwaddr.h" as: hwaddr is the type of a physical address (its size can be different from 'target_ulong'). All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: $ fgrep define include/exec/hwaddr.h #define HWADDR_H #define HWADDR_BITS 64 #define HWADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 ^^^^^^ #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 #define HWADDR_PRIu PRIu64 #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 Since hwaddr's size can be *different* from target_ulong, it is very confusing to read one of its format using the 'TARGET_FMT_' prefix, normally used for the target_long / target_ulong types: $ fgrep TARGET_FMT_ include/exec/cpu-defs.h #define TARGET_FMT_lx "%08x" #define TARGET_FMT_ld "%d" #define TARGET_FMT_lu "%u" #define TARGET_FMT_lx "%016" PRIx64 #define TARGET_FMT_ld "%" PRId64 #define TARGET_FMT_lu "%" PRIu64 Apparently this format was missed during commit a8170e5e97 ("Rename target_phys_addr_t to hwaddr"), so complete it by doing a bulk-rename with: $ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230110212947.34557-1-philmd@linaro.org> [thuth: Fix some warnings from checkpatch.pl along the way] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-18target/ppc: Implement ISA 3.00 tlbie[l]Leandro Lupori1-0/+154
This initial version supports the invalidation of one or all TLB entries. Flush by PID/LPID, or based in process/partition scope is not supported, because it would make using the generic QEMU TLB implementation hard. In these cases, all entries are flushed. Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220712193741.59134-3-leandro.lupori@eldorado.org.br> [danielhb: moved 'set' declaration to TLBIE_RIC_PWC block] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: Remove msr_cm macroVíctor Colombo1-1/+1
msr_cm macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-14-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: Remove msr_gs macroVíctor Colombo1-2/+2
msr_gs macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-12-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-02-09target/ppc: Remove PowerPC 601 CPUsCédric Le Goater1-84/+0
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations. There is not much interest in keeping the CPU model of this POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of the 60x family which implement the complete PowerPC instruction set. Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203142756.1302515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-28ppc/ppc405: Fix TLB flushingCédric Le Goater1-1/+11
Commit cd0c6f473532 did not take into account 405 CPUs when adding support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH flag when the SPR_40x_PID is set or a TLB updated. Cc: Thomas Huth <thuth@redhat.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113180352.1234512-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater1-52/+45
There is no need to deactivate MMU logging at compile time. Remove all use of defines. Only keep DUMP_PAGE_TABLES for another series since page tables could be dumped from the monitor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: remove 401/403 CPUsCédric Le Goater1-1/+0
They have been there since 2007 without any board using them, most were protected by a TODO define. Drop support. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211202191108.1291515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Remove the software TLB model of 7450 CPUsFabiano Rosas1-31/+0
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448) The QEMU-side software TLB implementation for the 7450 family of CPUs is being removed due to lack of known users in the real world. The last users in the code were removed by the two previous commits. A brief history: The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU models in switches...") with the mention that Linux was not able to handle the TLB miss interrupts and the MMU model would be kept disabled. At some point later, commit 8ca3f6c382 ("Allow selection of all defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450 family without further justification. We have since the year 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. Attempts were made to find a guest OS that implemented the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. All CPUs that registered this feature were moved to an MMU model that replaces the software TLB with a QEMU hardware TLB implementation. They can now run the same software as the 7400 CPUs, including the OSes mentioned above. References: - https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 - https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-11ppc/mmu_helper.c: do not truncate 'ea' in booke206_invalidate_ea_tlb()Daniel Henrique Barboza1-1/+1
'tlbivax' is implemented by gen_tlbivax_booke206() via gen_helper_booke206_tlbivax(). In case the TLB needs to be flushed, booke206_invalidate_ea_tlb() is called. All these functions, but booke206_invalidate_ea_tlb(), uses a 64-bit effective address 'ea'. booke206_invalidate_ea_tlb() uses an uint32_t 'ea' argument that truncates the original 'ea' value for apparently no particular reason. This function retrieves the tlb pointer by calling booke206_get_tlbm(), which also uses a target_ulong address as parameter - in this case, a truncated 'ea' address. All the surrounding logic considers the effective TLB address as a 64 bit value, aside from the signature of booke206_invalidate_ea_tlb(). Last but not the least, PowerISA 2.07B section 6.11.4.9 [2] makes it clear that the effective address "EA" is a 64 bit value. Commit 01662f3e5133 introduced this code and no changes were made ever since. An user detected a problem with tlbivax [1] stating that this address truncation was the cause. This same behavior might be the source of several subtle bugs that were never caught. For all these reasons, this patch assumes that this address truncation is the result of a mistake/oversight of the original commit, and changes booke206_invalidate_ea_tlb() 'ea' argument to 'vaddr'. [1] https://gitlab.com/qemu-project/qemu/-/issues/52 [2] https://wiki.raptorcs.com/wiki/File:PowerISA_V2.07B.pdf Fixes: 01662f3e5133 ("PPC: Implement e500 (FSL) MMU") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/52 Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-08-27target/ppc: divided mmu_helper.c in 2 filesLucas Mateus Castro (alqotel)1-1589/+1
Divided mmu_helper.c in 2 files, functions inside #ifdef CONFIG_SOFTMMU stayed in mmu_helper.c, other functions moved to mmu_common.c. Updated meson.build to compile mmu_common.c and only compile mmu_helper.c when CONFIG_TCG is set. Moved function declarations, #define and structs used by both files to internal.h except for functions that use structures defined in cpu.h, those were moved to cpu.h. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210723175627.72847-2-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Don't compile ppc_tlb_invalid_all without TCGLucas Mateus Castro (alqotel)1-0/+4
The function ppc_tlb_invalid_all is not compiled anymore in a TCG-less environment, and the call to that function has been disabled in this situation Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210708164957.28096-2-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: change ppc_hash32_xlate to use mmu_idxBruno Larsen (billionai)1-1/+1
Changed hash32 address translation to use the supplied mmu_idx, instead of using what was stored in the msr, for parity purposes (radix64 already uses that) and for conceptual correctness, all the relevant functions should always use the supplied mmu_idx, as there are no guarantees that the mmu_idx stored in the CPU variable will not desync. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210706150316.21005-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: changed ppc_hash64_xlate to use mmu_idxBruno Larsen (billionai)1-1/+1
Changed hash64 address translation to use the supplied mmu_idx instead of using the one stored in the msr, for parity purposes (other book3s MMUs already use it). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210628133610.1143-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: fix address translation bug for radix mmusBruno Larsen (billionai)1-3/+5
This commit attempts to fix a technical hiccup first mentioned by Richard Henderson in https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html To sumarize the hiccup here, when radix-style mmus are translating an address, they might need to call a second level of translation, with hypervisor privileges. However, the way it was being done up until this point meant that the second level translation had the same privileges as the first level. It could lead to a bug in address translation when running KVM inside a TCG guest, but this bug was never experienced by users, so this isn't as much a bug fix as it is a correctness cleanup. This patch attempts that cleanup by making radix64_*_xlate functions receive the mmu_idx, and passing one with the correct permission for the second level translation. The mmuidx macros added by this patch are only correct for non-bookE mmus, because BookE style set the IS and DS bits inverted and there might be other subtle differences. However, there doesn't seem to be BookE cpus that have radix-style mmus, so we left a comment there to document the issue, in case a machine does have that and was missed. As part of this cleanup, we now need to send the correct mmmu_idx when calling get_phys_page_debug, otherwise we might not be able to see the memory that the CPU could Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210628133610.1143-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Fix compilation with FLUSH_ALL_TLBS debug optionFabiano Rosas1-8/+0
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu': ../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu' [-Werror=unused-variable] 1802 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_dbatu': ../target/ppc/mmu_helper.c:1838:17: error: unused variable 'cpu' [-Werror=unused-variable] 1838 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_601_batu': ../target/ppc/mmu_helper.c:1874:17: error: unused variable 'cpu' [-Werror=unused-variable] 1874 | PowerPCCPU *cpu = env_archcpu(env); | ^~~ ../target/ppc/mmu_helper.c: In function 'helper_store_601_batl': ../target/ppc/mmu_helper.c:1919:17: error: unused variable 'cpu' [-Werror=unused-variable] 1919 | PowerPCCPU *cpu = env_archcpu(env); Fixes: db70b31144 ("target/ppc: Use env_cpu, env_archcpu") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210702215235.1941771-3-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Fix compilation with DUMP_PAGE_TABLES debug optionFabiano Rosas1-1/+1
../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb': ../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of 'ppc_hash32_hpt_mask' from incompatible pointer type [-Werror=incompatible-pointer-types] 514 | ppc_hash32_hpt_mask(env) + 0x80); | ^~~ | | | CPUPPCState * Fixes: 36778660d7 ("target/ppc: Eliminate htab_base and htab_mask variables") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210702215235.1941771-2-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Restrict ppc_cpu_tlb_fill to TCGRichard Henderson1-0/+2
This function is used by TCGCPUOps, and is thus TCG specific. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-10-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Introduce ppc_xlateRichard Henderson1-63/+37
Create one common dispatch for all of the ppc_*_xlate functions. Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate and ppc_hash64_xlate. Remove the separate *_handle_mmu_fault and *_get_phys_page_debug functions, using common code for ppc_cpu_tlb_fill and ppc_cpu_get_phys_page_debug. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-9-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Split out ppc_jumbo_xlateRichard Henderson1-83/+96
Mirror the interface of ppc_radix64_xlate (mostly), putting all of the logic for older mmu translation into a single entry point. For booke, we need to add mmu_idx to the xlate-style interface. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-8-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-09target/ppc: Remove PowerPCCPUClass.handle_mmu_faultRichard Henderson1-4/+20
Instead, use a switch on env->mmu_model. This avoids some replicated information in cpu setup. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-2-bruno.larsen@eldorado.org.br> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: added ifdefs around TCG-only codeBruno Larsen (billionai)1-2/+14
excp_helper.c, mmu-hash64.c and mmu_helper.c have some function declarations that are TCG-only, and couldn't be easily moved to a TCG only file, so ifdefs were added around them. We also needed ifdefs around some header files because helper-proto.h includes trace/generated-helpers.h, which is never created when building without TCG, and cpu_ldst.h includes tcg/tcg.h, whose containing folder is not included as a -iquote. As future cleanup, we could change the part of the configuration script to add those. cpu_init.c also had a callback definition that is TCG only and could be removed as part of a future cleanup (all the dump_statistics part is almost never used and will become obsolete as we transition to using decodetree). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210525115355.8254-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: fold ppc_store_ptcr into it's only callerBruno Larsen (billionai)1-28/+0
ppc_store_ptcr, defined in mmu_helper.c, was only used by helper_store_ptcr, in misc_helper.c. To avoid possible confusion, the function was folded into the helper. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526143516.125582-1-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument for mmubooke206_get_physical_addressRichard Henderson1-2/+2
It is no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-16-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from mmubooke206_check_tlbRichard Henderson1-31/+15
We can now use MMU_INST_FETCH from access_type for this. Unify the I/D code paths, making use of prot_for_access_type. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-15-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from mmubooke_get_physical_addressRichard Henderson1-4/+2
It is no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-14-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from mmubooke_check_tlbRichard Henderson1-31/+13
We can now use MMU_INST_FETCH from access_type for this. Unify the I/D code paths, making use of prot_for_access_type. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-13-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from mmu40x_get_physical_addressRichard Henderson1-4/+2
It is no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-12-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from get_bat_6xx_tlbRichard Henderson1-11/+8
We can now use MMU_INST_FETCH from access_type for this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-11-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from ppc6xx_tlb_checkRichard Henderson1-6/+4
We can now use MMU_INST_FETCH from access_type for this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-10-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from ppc6xx_tlb_pte_checkRichard Henderson1-2/+2
It is no longer used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-9-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Remove type argument from check_protRichard Henderson1-27/+6
We can now use MMU_INST_FETCH from access_type for this. Use prot_for_access_type to simplify everything. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-8-richard.henderson@linaro.org> [dwg: Remove a stray trailing whitespace] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Use MMUAccessType in mmu_helper.cRichard Henderson1-76/+85
This replaces 'int rw' with 'MMUAccessType access_type'. Comparisons vs zero become either MMU_DATA_LOAD or MMU_DATA_STORE, since we had previously squashed rw to 0 for code access. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-7-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: Rename access_type to type in mmu_helper.cRichard Henderson1-32/+32
The variable that holds ACCESS_INT, ACCESS_FLOAT, etc is variously called 'int type' or 'int access_type' within this file. Standardize on 'int type' throughout. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-6-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-05-19target/ppc: moved ppc_store_sdr1 to cpu.cBruno Larsen (billionai)1-26/+0
Moved this function that is required in !TCG cases into a common code file Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210512140813.112884-3-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Fixed compile error with linux-user targets] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14target/ppc: Introduce an mmu_is_64bit() helperGreg Kurz1-5/+5
Callers don't really need to know how 64-bit MMU model enums are computed. Hide this in a helper. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20201209173536.1437351-3-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14target/ppc: replaced the TODO with LOG_UNIMP and add break for silence warningsChen Qun1-2/+3
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/ppc/mmu_helper.c: In function ‘dump_mmu’: target/ppc/mmu_helper.c:1351:12: warning: this statement may fall through [-Wimplicit-fallthrough=] 1351 | if (ppc64_v3_radix(env_archcpu(env))) { | ^ target/ppc/mmu_helper.c:1358:5: note: here 1358 | default: | ^~~~~~~ Use "qemu_log_mask(LOG_UNIMP**)" instead of the TODO comment. And add the break statement to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201116024810.2415819-8-kuhn.chenqun@huawei.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-11-15powerpc tcg: Fix Lesser GPL version numberChetan Pant1-1/+1
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201019061126.3102-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-10-28ppc/: fix some comment spelling errorszhaolichang1-2/+2
I found that there are many spelling errors in the comments of qemu/target/ppc. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20201009064449.2336-3-zhaolichang@huawei.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-15target: Remove unnecessary CPU() castPhilippe Mathieu-Daudé1-1/+1
The CPU() macro is defined as: #define CPU(obj) ((CPUState *)(obj)) which expands to: ((CPUState *)object_dynamic_cast_assert((Object *)(obj), (name), __FILE__, __LINE__, __func__)) This assertion can only fail when @obj points to something other than its stated type, i.e. when we're in undefined behavior country. Remove the unnecessary CPU() casts when we already know the pointer is of CPUState type. Patch created mechanically using spatch with this script: @@ typedef CPUState; CPUState *s; @@ - CPU(s) + s Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200512070020.22782-2-f4bug@amsat.org>
2019-08-21target/ppc: Rewrite a fall through commentPhilippe Mathieu-Daudé1-3/+3
GCC9 is confused by this comment when building with CFLAG -Wimplicit-fallthrough=2: target/ppc/mmu_helper.c: In function ‘dump_mmu’: target/ppc/mmu_helper.c:1349:12: error: this statement may fall through [-Werror=implicit-fallthrough=] 1349 | if (ppc64_v3_radix(env_archcpu(env))) { | ^ target/ppc/mmu_helper.c:1356:5: note: here 1356 | default: | ^~~~~~~ cc1: all warnings being treated as errors Rewrite the comment using 'fall through' which is recognized by GCC and static analyzers. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190719131425.10835-6-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-08-16Include qemu/main-loop.h lessMarkus Armbruster1-0/+2
In my "build everything" tree, changing qemu/main-loop.h triggers a recompile of some 5600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). It includes block/aio.h, which in turn includes qemu/event_notifier.h, qemu/notify.h, qemu/processor.h, qemu/qsp.h, qemu/queue.h, qemu/thread-posix.h, qemu/thread.h, qemu/timer.h, and a few more. Include qemu/main-loop.h only where it's needed. Touching it now recompiles only some 1700 objects. For block/aio.h and qemu/event_notifier.h, these numbers drop from 5600 to 2800. For the others, they shrink only slightly. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190812052359.30071-21-armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-06-10target/ppc: Use env_cpu, env_archcpuRichard Henderson1-68/+47
Cleanup in the boilerplate that each target must define. Replace ppc_env_get_cpu with env_archcpu. The combination CPU(ppc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-1/+1
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-6/+0
We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/ppc: Convert to CPUClass::tlb_fillRichard Henderson1-9/+13
Cc: qemu-ppc@nongnu.org Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-12-27 20:01:52 +0000