| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-03-01 | target/ppc: introduce helper_update_ov_legacy | Nikunj A Dadhania | 1 | -21/+13 |
| 2017-01-31 | ppc: Implement bcdutrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+51 |
| 2017-01-31 | ppc: Implement bcdtrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+37 |
| 2017-01-31 | ppc: Implement bcdsr. instruction | Jose Ricardo Ziviani | 1 | -0/+48 |
| 2017-01-31 | ppc: Implement bcdus. instruction | Jose Ricardo Ziviani | 1 | -0/+41 |
| 2017-01-31 | ppc: Implement bcds. instruction | Jose Ricardo Ziviani | 1 | -0/+40 |
| 2017-01-31 | ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro | Jose Ricardo Ziviani | 1 | -3/+3 |
| 2017-01-31 | target-ppc: Add xxinsertw instruction | Nikunj A Dadhania | 1 | -0/+25 |
| 2017-01-31 | target-ppc: Add xxextractuw instruction | Nikunj A Dadhania | 1 | -0/+26 |
| 2017-01-31 | target-ppc: Implement bcd_is_valid function | Jose Ricardo Ziviani | 1 | -7/+20 |
| 2017-01-31 | target-ppc: add vextu[bhw][lr]x instructions | Avinesh Kumar | 1 | -0/+36 |
| 2017-01-31 | target-ppc: Implement bcdsetsgn. instruction | Jose Ricardo Ziviani | 1 | -0/+19 |
| 2017-01-31 | target-ppc: Implement bcdcpsgn. instruction | Jose Ricardo Ziviani | 1 | -0/+23 |
| 2017-01-31 | target-ppc: Implement bcdctsq. instruction | Jose Ricardo Ziviani | 1 | -0/+40 |
| 2017-01-31 | target-ppc: Implement bcdcfsq. instruction | Jose Ricardo Ziviani | 1 | -0/+38 |
| 2017-01-31 | target-ppc: rename CRF_* defines as CRF_*_BIT | Nikunj A Dadhania | 1 | -15/+15 |
| 2017-01-10 | target-ppc: Use ctpop helper | Richard Henderson | 1 | -15/+3 |
| 2017-01-10 | target-ppc: Use clz and ctz opcodes | Richard Henderson | 1 | -20/+0 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+3126 |
