Age | Commit message (Expand) | Author | Files | Lines |
2021-07-13 | target/openrisc: Cache constant 0 in DisasContext | Richard Henderson | 1 | -6/+6 |
2021-07-13 | target/openrisc: Use tcg_constant_tl for dc->R0 | Richard Henderson | 1 | -8/+2 |
2021-07-13 | target/openrisc: Use tcg_constant_* | Richard Henderson | 1 | -33/+9 |
2021-07-12 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into... | Peter Maydell | 1 | -8/+8 |
2021-07-09 | target/openrisc: Use translator_use_goto_tb | Richard Henderson | 1 | -7/+8 |
2021-07-09 | tcg: Avoid including 'trace-tcg.h' in target translate.c | Philippe Mathieu-Daudé | 1 | -1/+0 |
2021-07-09 | meson: Introduce target-specific Kconfig | Philippe Mathieu-Daudé | 1 | -0/+2 |
2021-05-26 | hw/core: Constify TCGCPUOps | Richard Henderson | 1 | -1/+1 |
2021-05-26 | cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps | Philippe Mathieu-Daudé | 1 | -1/+1 |
2021-05-26 | cpu: Introduce SysemuCPUOps structure | Philippe Mathieu-Daudé | 1 | -0/+8 |
2021-05-02 | Do not include sysemu/sysemu.h if it's not really necessary | Thomas Huth | 1 | -1/+0 |
2021-04-01 | target/openrisc: fix icount handling for timer instructions | Pavel Dovgalyuk | 1 | -0/+15 |
2021-02-05 | cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass | Claudio Fontana | 1 | -4/+13 |
2021-02-05 | cpu: move cc->do_interrupt to tcg_ops | Claudio Fontana | 1 | -1/+1 |
2021-02-05 | cpu: Move tlb_fill to tcg_ops | Eduardo Habkost | 1 | -1/+1 |
2021-02-05 | cpu: Move cpu_exec_* to tcg_ops | Eduardo Habkost | 1 | -1/+1 |
2021-02-05 | cpu: Introduce TCGCpuOperations struct | Eduardo Habkost | 1 | -1/+1 |
2020-12-19 | migration: Replace migration's JSON writer by the general one | Markus Armbruster | 1 | -1/+1 |
2020-12-15 | target/openrisc: Move pic_cpu code into CPU object proper | Peter Maydell | 2 | -1/+32 |
2020-11-17 | target/openrisc: Remove dead code attempting to check "is timer disabled" | Peter Maydell | 1 | -3/+0 |
2020-09-18 | qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros | Eduardo Habkost | 1 | -1/+1 |
2020-09-09 | Use OBJECT_DECLARE_TYPE where possible | Eduardo Habkost | 1 | -4/+2 |
2020-09-09 | Use DECLARE_*CHECKER* macros | Eduardo Habkost | 1 | -6/+2 |
2020-09-09 | Move QOM typedefs and add missing includes | Eduardo Habkost | 1 | -4/+7 |
2020-08-21 | meson: target | Paolo Bonzini | 4 | -17/+25 |
2020-08-21 | meson: rename included C source files to .c.inc | Paolo Bonzini | 3 | -5/+5 |
2020-05-19 | softfloat: Name compare relation enum | Richard Henderson | 1 | -2/+2 |
2020-03-19 | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ... | Peter Maydell | 2 | -5/+5 |
2020-03-17 | cpu: Use DeviceClass reset instead of a special CPUClass reset | Peter Maydell | 2 | -5/+5 |
2020-03-17 | gdbstub: extend GByteArray to read register helpers | Alex Bennée | 2 | -2/+2 |
2020-01-24 | cpu: Use cpu_class_set_parent_reset() | Greg Kurz | 1 | -2/+1 |
2020-01-17 | Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging | Peter Maydell | 1 | -1/+1 |
2020-01-16 | target/openrisc: Fix FPCSR mask to allow setting DZF | Stafford Horne | 1 | -1/+1 |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 1 | -1/+1 |
2019-10-28 | target/openrisc: fetch code with translator_ld | Emilio G. Cota | 1 | -1/+1 |
2019-09-04 | target/openrisc: Update cpu "any" to v1.3 | Richard Henderson | 1 | -1/+1 |
2019-09-04 | target/openrisc: Implement l.adrp | Richard Henderson | 3 | -0/+16 |
2019-09-04 | target/openrisc: Implement move to/from FPCSR | Richard Henderson | 5 | -5/+38 |
2019-09-04 | target/openrisc: Implement unordered fp comparisons | Richard Henderson | 5 | -0/+145 |
2019-09-04 | target/openrisc: Add support for ORFPX64A32 | Richard Henderson | 6 | -3/+332 |
2019-09-04 | target/openrisc: Check CPUCFG_OF32S for float insns | Richard Henderson | 2 | -50/+36 |
2019-09-04 | target/openrisc: Fix lf.ftoi.s | Richard Henderson | 1 | -1/+1 |
2019-09-04 | target/openrisc: Add VR2 and AVR special processor registers | Richard Henderson | 3 | -6/+19 |
2019-09-04 | target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init | Richard Henderson | 3 | -13/+22 |
2019-09-04 | target/openrisc: Make VR and PPC read-only | Richard Henderson | 2 | -12/+1 |
2019-09-04 | target/openrisc: Cache R0 in DisasContext | Richard Henderson | 1 | -7/+12 |
2019-09-04 | target/openrisc: Replace cpu register array with a function | Richard Henderson | 1 | -97/+116 |
2019-09-04 | target/openrisc: Add DisasContext parameter to check_r0_write | Richard Henderson | 1 | -47/+49 |
2019-09-03 | tcg: TCGMemOp is now accelerator independent MemOp | Tony Nguyen | 1 | -2/+2 |
2019-08-21 | hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ | Markus Armbruster | 1 | -1/+1 |