riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-06-04	Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...	Peter Maydell	1	-3/+3
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	1	-3/+3
2018-06-01	target: Do not include "exec/exec-all.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-05-14	target/openrisc: Merge disas_openrisc_insn	Richard Henderson	1	-9/+4
2018-05-14	target/openrisc: Convert dec_float	Richard Henderson	2	-230/+149
2018-05-14	target/openrisc: Convert dec_compi	Richard Henderson	2	-58/+70
2018-05-14	target/openrisc: Convert dec_comp	Richard Henderson	2	-62/+73
2018-05-14	target/openrisc: Convert dec_M	Richard Henderson	2	-28/+16
2018-05-14	target/openrisc: Convert dec_logic	Richard Henderson	2	-36/+32
2018-05-14	target/openrisc: Convert dec_mac	Richard Henderson	2	-33/+27
2018-05-14	target/openrisc: Convert dec_calc	Richard Henderson	2	-169/+229
2018-05-14	target/openrisc: Convert remainder of dec_misc insns	Richard Henderson	2	-153/+141
2018-05-14	target/openrisc: Convert memory insns	Richard Henderson	2	-139/+160
2018-05-14	target/openrisc: Convert branch insns	Richard Henderson	2	-78/+84
2018-05-14	target/openrisc: Start conversion to decodetree.py	Richard Henderson	3	-43/+78
2018-05-14	target-openrisc: Write back result before FPE exception	Richard Henderson	3	-252/+126
2018-05-09	target/openrisc: convert to TranslatorOps	Emilio G. Cota	1	-84/+79
2018-05-09	target/openrisc: convert to DisasContextBase	Emilio G. Cota	1	-47/+46
2018-04-11	icount: fix cpu_restore_state_from_tb for non-tb-exit cases	Pavel Dovgalyuk	1	-4/+4
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov	1	-2/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	2	-1/+1
2018-02-05	qdev: use device_class_set_parent_realize/unrealize/reset()	Philippe Mathieu-Daudé	1	-3/+2
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	3	-8/+8
2017-12-27	target/*helper: don't check retaddr before calling cpu_restore_state	Alex Bennée	1	-5/+1
2017-12-18	misc: remove duplicated includes	Philippe Mathieu-Daudé	1	-1/+0
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	2	-46/+26
2017-10-27	openrisc: cleanup cpu type name composition	Igor Mammedov	2	-46/+26
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-3/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-3/+3
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-6/+1
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	4	-5/+5
2017-10-21	target/openrisc: Make coreid and numcores variable	Stafford Horne	1	-2/+3
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-4/+0
2017-09-06	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova	1	-0/+6
2017-09-01	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov	2	-8/+1
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-2/+2
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	5	-1/+28
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne	2	-28/+5
2017-05-04	target/openrisc: Implement full vmstate serialization	Stafford Horne	1	-2/+71
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	6	-10/+33
2017-05-04	target/openrisc: add numcores and coreid support	Stafford Horne	1	-0/+6
2017-05-04	target/openrisc: Fixes for memory debugging	Stafford Horne	1	-4/+20
2017-04-21	target/openrisc: Implement EPH bit	Tim 'mithro' Ansell	1	-0/+3
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	4	-1/+21
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson	3	-23/+66
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	5	-35/+25