riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	7	-74/+96
2017-02-14	target/openrisc: Invert the decoding in dec_calc	Richard Henderson	1	-207/+95
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	3	-12/+18
2017-02-14	target/openrisc: Streamline arithmetic and OVE	Richard Henderson	5	-314/+191
2017-02-14	target/openrisc: Rationalize immediate extraction	Richard Henderson	1	-58/+40
2017-02-14	target/openrisc: Tidy insn dumping	Richard Henderson	1	-24/+12
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	7	-8/+81
2017-02-14	target/openrisc: Fix exception handling status registers	Stafford Horne	1	-0/+7
2017-02-14	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson	1	-1/+1
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	3	-3/+3
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	2	-8/+4
2017-01-10	target-openrisc: Use clz and ctz opcodes	Richard Henderson	3	-23/+4
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	17	-0/+3868